Add support for PSL onehot/onehot0 functions (#1633)

* vhdl: parse PSL onehot/onehot0 builtin calls.  For #662

* update pyGHDL bindings

* Synthesis of PSL built-in onehot/onehot0 function.

* testsuite/synth: add tests of PSL built-in functions onehot()/onehot0() for #662

* doc: add info about PSL built-in functions onehot()/onehot0() for #662

* synth: refactor synthesis of onehot/onehot0 functions

Co-authored-by: eine <eine@users.noreply.github.com>

5 files changed, 194 insertions, 1 deletions

diff --git a/testsuite/synth/issue662/psl_onehot.vhdl b/testsuite/synth/issue662/psl_onehot.vhdl
new file mode 100644
index 000000000..feaa784df
--- /dev/null
+++ b/testsuite/synth/issue662/psl_onehot.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity psl_onehot is
+  port (clk  : in std_logic;
+        a, b : in std_logic_vector(3 downto 0);
+        c    : in natural range 0 to 15
+  );
+end entity psl_onehot;
+
+
+architecture psl of psl_onehot is
+begin
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  ONEHOT_0_a : assert always onehot(a);
+
+  -- This assertion fails at cycle 12
+  ONEHOT_1_a : assert always onehot(b);
+
+  -- This assertion fails at cycle 12
+  ONEHOT_2_a : assert always onehot(c);
+
+end architecture psl;
diff --git a/testsuite/synth/issue662/psl_onehot0.vhdl b/testsuite/synth/issue662/psl_onehot0.vhdl
new file mode 100644
index 000000000..edd4361c8
--- /dev/null
+++ b/testsuite/synth/issue662/psl_onehot0.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity psl_onehot0 is
+  port (clk  : in std_logic;
+        a, b : in std_logic_vector(3 downto 0);
+        c    : in natural range 0 to 15
+  );
+end entity psl_onehot0;
+
+
+architecture psl of psl_onehot0 is
+begin
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  ONEHOT0_0_a : assert always onehot0(a);
+
+  -- This assertion fails at cycle 15
+  ONEHOT0_1_a : assert always onehot0(b);
+
+  -- This assertion fails at cycle 15
+  ONEHOT0_2_a : assert always onehot(c);
+
+end architecture psl;
diff --git a/testsuite/synth/issue662/tb_psl_onehot.vhdl b/testsuite/synth/issue662/tb_psl_onehot.vhdl
new file mode 100644
index 000000000..10b5d8c73
--- /dev/null
+++ b/testsuite/synth/issue662/tb_psl_onehot.vhdl
@@ -0,0 +1,69 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity tb_psl_onehot is
+end entity tb_psl_onehot;
+
+
+architecture psl of tb_psl_onehot is
+
+  procedure seq (s : string; signal clk : std_logic; signal o : out std_logic)
+  is
+  begin
+    for i in s'range loop
+      wait until rising_edge(clk);
+      case s(i) is
+        when '0' | '_' => o <= '0';
+        when '1' | '-' => o <= '1';
+        when others    => o <= 'X';
+      end case;
+    end loop;
+    wait;
+  end seq;
+
+  procedure hseq (s : string; signal clk : std_logic; signal o : out std_logic_vector(3 downto 0))
+  is
+  begin
+    for i in s'range loop
+      wait until rising_edge(clk);
+      case s(i) is
+        when '0' | '_' => o <= x"0";
+        when '1'       => o <= x"1";
+        when '2'       => o <= x"2";
+        when '3'       => o <= x"3";
+        when '4'       => o <= x"4";
+        when '5'       => o <= x"5";
+        when '6'       => o <= x"6";
+        when '7'       => o <= x"7";
+        when '8'       => o <= x"8";
+        when '9'       => o <= x"9";
+        when 'a' | 'A' => o <= x"A";
+        when 'b' | 'B' => o <= x"B";
+        when 'c' | 'C' => o <= x"C";
+        when 'd' | 'D' => o <= x"D";
+        when 'e' | 'E' => o <= x"E";
+        when 'f' | 'F' | '-' => o <= x"F";
+        when others => o <= x"X";
+      end case;
+    end loop;
+    wait;
+  end hseq;
+
+  signal a, b : std_logic_vector(3 downto 0) := x"0";
+  signal c    : natural range 0 to 15 := 0;
+  signal clk  : std_logic := '1';
+
+begin
+
+  dut: entity work.psl_onehot port map (clk, a, b, c);
+
+  clk <= not clk after 500 ps;
+
+  --             012345678901234
+  SEQ_A : hseq ("111222444888888", clk, a);
+  SEQ_B : hseq ("111222444888999", clk, b);
+
+  c <= to_integer(unsigned(b));
+
+end architecture psl;
diff --git a/testsuite/synth/issue662/tb_psl_onehot0.vhdl b/testsuite/synth/issue662/tb_psl_onehot0.vhdl
new file mode 100644
index 000000000..2f51ba020
--- /dev/null
+++ b/testsuite/synth/issue662/tb_psl_onehot0.vhdl
@@ -0,0 +1,69 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity tb_psl_onehot0 is
+end entity tb_psl_onehot0;
+
+
+architecture psl of tb_psl_onehot0 is
+
+  procedure seq (s : string; signal clk : std_logic; signal o : out std_logic)
+  is
+  begin
+    for i in s'range loop
+      wait until rising_edge(clk);
+      case s(i) is
+        when '0' | '_' => o <= '0';
+        when '1' | '-' => o <= '1';
+        when others    => o <= 'X';
+      end case;
+    end loop;
+    wait;
+  end seq;
+
+  procedure hseq (s : string; signal clk : std_logic; signal o : out std_logic_vector(3 downto 0))
+  is
+  begin
+    for i in s'range loop
+      wait until rising_edge(clk);
+      case s(i) is
+        when '0' | '_' => o <= x"0";
+        when '1'       => o <= x"1";
+        when '2'       => o <= x"2";
+        when '3'       => o <= x"3";
+        when '4'       => o <= x"4";
+        when '5'       => o <= x"5";
+        when '6'       => o <= x"6";
+        when '7'       => o <= x"7";
+        when '8'       => o <= x"8";
+        when '9'       => o <= x"9";
+        when 'a' | 'A' => o <= x"A";
+        when 'b' | 'B' => o <= x"B";
+        when 'c' | 'C' => o <= x"C";
+        when 'd' | 'D' => o <= x"D";
+        when 'e' | 'E' => o <= x"E";
+        when 'f' | 'F' | '-' => o <= x"F";
+        when others => o <= x"X";
+      end case;
+    end loop;
+    wait;
+  end hseq;
+
+  signal a, b : std_logic_vector(3 downto 0) := x"0";
+  signal c    : natural range 0 to 15 := 0;
+  signal clk  : std_logic := '1';
+
+begin
+
+  dut: entity work.psl_onehot0 port map (clk, a, b, c);
+
+  clk <= not clk after 500 ps;
+
+  --             012345678901234567
+  SEQ_A : hseq ("000111222444888888", clk, a);
+  SEQ_B : hseq ("000111222444888fff", clk, b);
+
+  c <= to_integer(unsigned(b));
+
+end architecture psl;
diff --git a/testsuite/synth/issue662/testsuite.sh b/testsuite/synth/issue662/testsuite.sh
index 5186799d1..cf8647e76 100755
--- a/testsuite/synth/issue662/testsuite.sh
+++ b/testsuite/synth/issue662/testsuite.sh
@@ -4,7 +4,7 @@
 
 GHDL_STD_FLAGS=--std=08
 
-for test in psl_prev psl_stable psl_rose psl_fell; do
+for test in psl_prev psl_stable psl_rose psl_fell psl_onehot psl_onehot0; do
   synth_analyze $test
   analyze tb_${test}.vhdl
   elab_simulate_failure tb_${test} --stop-time=20ns --asserts=disable-at-0 --assert-level=error