testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.

1 files changed, 0 insertions, 20 deletions

diff --git a/testsuite/synth/issue34/module.vhdl b/testsuite/synth/issue34/module.vhdl
deleted file mode 100644
index 67f3dd4b3..000000000
--- a/testsuite/synth/issue34/module.vhdl
+++ /dev/null
@@ -1,20 +0,0 @@
-library ieee;
-  use ieee.std_logic_1164.all;
-
-entity module is
-  port (
-    clk : in std_logic;
-    a : in std_logic_vector(7 downto 0);
-    b : out std_logic_vector(7 downto 0)
-  );
-end module;
-
-architecture rtl of module is
-begin
-  i_submodule : entity work.submodule
-  port map (
-    clk => clk,
-    a => a,
-    b => b
-  );
-end rtl;