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author | Tristan Gingold <tgingold@free.fr> | 2022-11-05 08:03:16 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-11-05 08:03:16 +0100 |
commit | 391714eeecaaa43259a7b5ef56a2c910104978c0 (patch) | |
tree | 948e7e92156ec8d3b865692baa7eb0baaf38cfa5 /testsuite/synth/issue2232/sipo.vhdl | |
parent | b590278e3b9ef81ea940118a2eec41f2bc0e0380 (diff) | |
download | ghdl-391714eeecaaa43259a7b5ef56a2c910104978c0.tar.gz ghdl-391714eeecaaa43259a7b5ef56a2c910104978c0.tar.bz2 ghdl-391714eeecaaa43259a7b5ef56a2c910104978c0.zip |
testsuite/synth: add a test for #2232
Diffstat (limited to 'testsuite/synth/issue2232/sipo.vhdl')
-rw-r--r-- | testsuite/synth/issue2232/sipo.vhdl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/issue2232/sipo.vhdl b/testsuite/synth/issue2232/sipo.vhdl new file mode 100644 index 000000000..adeb32054 --- /dev/null +++ b/testsuite/synth/issue2232/sipo.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sipo is + port (clk : in std_logic; + in_data : in std_logic; + out_data : out std_logic_vector(1 downto 0)); +end entity; + +architecture rtl of sipo is + signal mem : std_logic_vector(1 downto 0); + signal ctr : unsigned(0 downto 0); +begin + process (clk) begin + if rising_edge(clk) then +-- This indirection doesn't synthesize correctly. + mem(to_integer(ctr)) <= in_data; + + ctr(0) <= not ctr(0); + end if; + end process; + + out_data <= mem; +end architecture rtl; |