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author | Tristan Gingold <tgingold@free.fr> | 2022-07-26 22:02:34 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-07-26 22:02:34 +0200 |
commit | 3c1f8dc37a554bc5a5d087a6ae8253dc6021c9ed (patch) | |
tree | 929e637de2ab37b3696a64a6177a8655e0038974 /testsuite/synth/issue2140/bug.vhdl | |
parent | a123be70f01c43cdafd698d61eca1913db478d24 (diff) | |
download | ghdl-3c1f8dc37a554bc5a5d087a6ae8253dc6021c9ed.tar.gz ghdl-3c1f8dc37a554bc5a5d087a6ae8253dc6021c9ed.tar.bz2 ghdl-3c1f8dc37a554bc5a5d087a6ae8253dc6021c9ed.zip |
testsuite/synth: add a test for #2140
Diffstat (limited to 'testsuite/synth/issue2140/bug.vhdl')
-rw-r--r-- | testsuite/synth/issue2140/bug.vhdl | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/testsuite/synth/issue2140/bug.vhdl b/testsuite/synth/issue2140/bug.vhdl new file mode 100644 index 000000000..bfb18a550 --- /dev/null +++ b/testsuite/synth/issue2140/bug.vhdl @@ -0,0 +1,68 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity sub is + port ( + clk : in std_ulogic; + reset_n : in std_ulogic; + + src_valid : in std_ulogic; + src_ready : out std_ulogic + ); +end sub; + +architecture rtl of sub is +begin +end architecture; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is + port( + clk : in std_ulogic; + reset_n : in std_ulogic + ); +end bug; + +architecture struct of bug is + signal filtered_src_valid : std_ulogic; + signal filtered_src_ready : std_ulogic; + + signal pipeline_src_valid : std_ulogic; + signal pipeline_src_ready : std_ulogic; + + type state_t is (idle, active); + signal state : state_t; +begin + +pipeline_src_valid <= filtered_src_valid when (state = idle) or (state = active) else '0'; + +process(clk, reset_n) +begin + if reset_n = '0' then + elsif rising_edge(clk) then + if state = idle then + if filtered_src_valid = '1' and filtered_src_ready = '1' then + state <= active; + end if; + elsif state = active then + if pipeline_src_valid = '1' and pipeline_src_ready = '1' then + state <= idle; + end if; + end if; + end if; +end process; + +pipeline : entity work.sub + port map( + clk => clk, + reset_n => reset_n, + + src_valid => pipeline_src_valid, + src_ready => pipeline_src_ready + ); + +end architecture; |