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author | Tristan Gingold <tgingold@free.fr> | 2022-04-28 07:30:40 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-04-28 07:30:40 +0200 |
commit | 496dd0adacabcad79146f7beadefc9e938f8ef9f (patch) | |
tree | 6d5e45ec96d77c8b5db8685e5520c94c010918eb /testsuite/synth/issue2043/ent.vhdl | |
parent | 480b62181dd3e7d9e598de5672e1aa471d9355f9 (diff) | |
download | ghdl-496dd0adacabcad79146f7beadefc9e938f8ef9f.tar.gz ghdl-496dd0adacabcad79146f7beadefc9e938f8ef9f.tar.bz2 ghdl-496dd0adacabcad79146f7beadefc9e938f8ef9f.zip |
testsuite/synth: add a test for #2043
Diffstat (limited to 'testsuite/synth/issue2043/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue2043/ent.vhdl | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/issue2043/ent.vhdl b/testsuite/synth/issue2043/ent.vhdl new file mode 100644 index 000000000..5e8727a60 --- /dev/null +++ b/testsuite/synth/issue2043/ent.vhdl @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; + +entity ent is + generic ( + g_NumberOfChannels : natural := 4; + g_BitsPerChannel : natural := 16 + ); + port ( + CLK : in std_logic; + RST : in std_logic; + DATA : out std_logic_vector(g_NumberOfChannels*g_BitsPerChannel-1 downto 0) + ); +end entity; + +architecture arch of ent is + + signal do_out : STD_LOGIC_VECTOR(15 DOWNTO 0); + +begin + + process(RST, CLK) + variable cnt: natural range 0 to g_NumberOfChannels-1; + begin + if RST then + cnt := 0; + elsif rising_edge(CLK) then + DATA((cnt+1)*g_BitsPerChannel-1 downto cnt*g_BitsPerChannel) <= do_out(do_out'left downto 1+do_out'left-g_BitsPerChannel); + cnt := cnt + 1 when cnt<g_NumberOfChannels-1 else 0; + end if; + end process; + +end architecture; |