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author | Tristan Gingold <tgingold@free.fr> | 2021-10-13 20:21:52 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-10-13 20:21:52 +0200 |
commit | 37a7c43bab3917d0e1ba4a78c6e3957fcbff3771 (patch) | |
tree | efad2d602cdc7d9760db5c9608d5fcc0aaec864d /testsuite/synth/issue1889/shiftmux2.vhdl | |
parent | ff3105a7a8b8298771c64fd13171e33385f6fcc8 (diff) | |
download | ghdl-37a7c43bab3917d0e1ba4a78c6e3957fcbff3771.tar.gz ghdl-37a7c43bab3917d0e1ba4a78c6e3957fcbff3771.tar.bz2 ghdl-37a7c43bab3917d0e1ba4a78c6e3957fcbff3771.zip |
testsuite/synth: add a test for #1889
Diffstat (limited to 'testsuite/synth/issue1889/shiftmux2.vhdl')
-rw-r--r-- | testsuite/synth/issue1889/shiftmux2.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue1889/shiftmux2.vhdl b/testsuite/synth/issue1889/shiftmux2.vhdl new file mode 100644 index 000000000..619469500 --- /dev/null +++ b/testsuite/synth/issue1889/shiftmux2.vhdl @@ -0,0 +1,21 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity shiftMux2 is + Port ( + clk : in std_logic; + --inputA + inputA : in std_logic; + outputB : out std_logic + ); +end shiftMux2; + +architecture Rtl of shiftMux2 is +begin + process (clk) is + begin + if rising_edge(clk) then + outputB <= inputA; + end if; + end process; +end Rtl; |