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author | Tristan Gingold <tgingold@free.fr> | 2021-06-16 07:48:22 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-06-16 07:48:22 +0200 |
commit | 4c0f9967e541b914a207bd4419d62d00d3e1745c (patch) | |
tree | 8d5edcededa4d1aa4d167cffcbaceca6aae3e596 /testsuite/synth/issue1781/imem2.vhdl | |
parent | 9a913ec7ac5bc2193ec3df90bf7f43808f5c80c6 (diff) | |
download | ghdl-4c0f9967e541b914a207bd4419d62d00d3e1745c.tar.gz ghdl-4c0f9967e541b914a207bd4419d62d00d3e1745c.tar.bz2 ghdl-4c0f9967e541b914a207bd4419d62d00d3e1745c.zip |
testsuite/synth: add test for #1781
Diffstat (limited to 'testsuite/synth/issue1781/imem2.vhdl')
-rw-r--r-- | testsuite/synth/issue1781/imem2.vhdl | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/testsuite/synth/issue1781/imem2.vhdl b/testsuite/synth/issue1781/imem2.vhdl new file mode 100644 index 000000000..13d60dd5a --- /dev/null +++ b/testsuite/synth/issue1781/imem2.vhdl @@ -0,0 +1,104 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity imem2 is + generic ( + IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000" + ); + port ( + clk_i : in std_ulogic; + rden_i : in std_ulogic; + wren_i : in std_ulogic; + ben_i : in std_ulogic_vector(03 downto 0); + addr_i : in std_ulogic_vector(31 downto 0); + data_i : in std_ulogic_vector(31 downto 0); + data_o : out std_ulogic_vector(31 downto 0); + ack_o : out std_ulogic + ); +end entity; + +architecture ok of imem2 is + signal addr : std_ulogic_vector(15 downto 0); + type ram_t is array(0 to 2**15-1) of std_ulogic_vector(31 downto 0); + signal acc_en : std_ulogic; + constant abb_c : std_logic_vector(31 downto 16) := (others=>'0'); +begin + addr <= addr_i(addr'left+2 downto 2); -- word aligned + acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range); + process(clk_i) + variable memory : ram_t; + begin + if rising_edge(clk_i) then + if acc_en then + ack_o <= rden_i or wren_i; + end if; + if acc_en and wren_i then + for x in 0 to 3 loop + if ben_i(x) then + memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8); + end if; + end loop; + end if; + if acc_en and rden_i then + data_o <= memory(to_integer(unsigned(addr))); + end if; + end if; + end process; +end architecture; + +architecture notok of imem2 is + signal addr : std_ulogic_vector(7 downto 0); + type ram_t is array(0 to 2**8-1) of std_ulogic_vector(31 downto 0); + signal acc_en : std_ulogic; + constant abb_c : std_logic_vector(31 downto 16) := (others=>'0'); +begin + addr <= addr_i(addr'left+2 downto 2); -- word aligned + acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range); + process(clk_i) + variable memory : ram_t; + begin + if rising_edge(clk_i) and acc_en='1' then + ack_o <= rden_i or wren_i; + if wren_i then + for x in 0 to 3 loop + if ben_i(x) then + memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8); + end if; + end loop; + end if; + if rden_i then + data_o <= memory(to_integer(unsigned(addr))); + end if; + end if; + end process; +end architecture; + +architecture neitherok of imem2 is + signal addr : std_ulogic_vector(15 downto 0); + type ram_t is array(0 to 2**15-1) of std_ulogic_vector(31 downto 0); + signal acc_en : std_ulogic; + constant abb_c : std_logic_vector(31 downto 16) := (others=>'0'); + begin + addr <= addr_i(addr'left+2 downto 2); -- word aligned + acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range); + process(clk_i) + variable memory : ram_t; + begin + if rising_edge(clk_i) then + if acc_en then + ack_o <= rden_i or wren_i; + if wren_i then + for x in 0 to 3 loop + if ben_i(x) then + memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8); + end if; + end loop; + end if; + if rden_i then + data_o <= memory(to_integer(unsigned(addr))); + end if; + end if; + end if; + end process; + end architecture; |