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| author | Tristan Gingold <tgingold@free.fr> | 2020-12-20 08:52:40 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-12-20 08:53:23 +0100 |
| commit | 8ed352778368cfbff239bb2a89fc6a937c65fc26 (patch) | |
| tree | 6cd0bcafeb0a9a165915a3422a2882b6af104c79 /testsuite/synth/issue1540/ent1.vhdl | |
| parent | c0c405faf6473da4911c05675bc8060971577699 (diff) | |
| download | ghdl-8ed352778368cfbff239bb2a89fc6a937c65fc26.tar.gz ghdl-8ed352778368cfbff239bb2a89fc6a937c65fc26.tar.bz2 ghdl-8ed352778368cfbff239bb2a89fc6a937c65fc26.zip | |
testsuite/synth: add tests for #1540
Diffstat (limited to 'testsuite/synth/issue1540/ent1.vhdl')
| -rw-r--r-- | testsuite/synth/issue1540/ent1.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/issue1540/ent1.vhdl b/testsuite/synth/issue1540/ent1.vhdl new file mode 100644 index 000000000..254f6014f --- /dev/null +++ b/testsuite/synth/issue1540/ent1.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent1 is + port ( + o: out bit + ); +end entity; + +architecture arch of ent1 is +begin + o <= to_bit(std_ulogic' ('L')); +end architecture; |