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authorTristan Gingold <tgingold@free.fr>2020-05-23 18:00:23 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-23 18:01:37 +0200
commit3e454e617c67184af75cb7e8fd6b22fa869703c1 (patch)
treee6d1b42b529fa3cf90fe53765f16c0706d16aa51 /testsuite/synth/issue1318/ram2.v
parent71cc7400561198ec1155f5980209cf79a5678074 (diff)
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testsuite/synth: add a test for #1318
Diffstat (limited to 'testsuite/synth/issue1318/ram2.v')
-rw-r--r--testsuite/synth/issue1318/ram2.v15
1 files changed, 15 insertions, 0 deletions
diff --git a/testsuite/synth/issue1318/ram2.v b/testsuite/synth/issue1318/ram2.v
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+++ b/testsuite/synth/issue1318/ram2.v
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+`default_nettype none
+module memory #(parameter W=8, D=64)
+ (input wire clk, wr_en,
+ input wire [W-1:0] wr_addr, rd_addr,
+ input wire [D-1:0] din,
+ output reg [D-1:0] dout);
+
+ (*ram_style = "block"*)
+ reg [D-1:0] mem [(1<<W)-1:0];
+
+ always @(posedge clk) begin
+ if(wr_en) mem[wr_addr] <= din;
+ dout <= mem[rd_addr];
+ end
+endmodule // memory