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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-23 18:00:23 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-23 18:01:37 +0200 |
| commit | 3e454e617c67184af75cb7e8fd6b22fa869703c1 (patch) | |
| tree | e6d1b42b529fa3cf90fe53765f16c0706d16aa51 /testsuite/synth/issue1318/ram1.v | |
| parent | 71cc7400561198ec1155f5980209cf79a5678074 (diff) | |
| download | ghdl-3e454e617c67184af75cb7e8fd6b22fa869703c1.tar.gz ghdl-3e454e617c67184af75cb7e8fd6b22fa869703c1.tar.bz2 ghdl-3e454e617c67184af75cb7e8fd6b22fa869703c1.zip | |
testsuite/synth: add a test for #1318
Diffstat (limited to 'testsuite/synth/issue1318/ram1.v')
| -rw-r--r-- | testsuite/synth/issue1318/ram1.v | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/testsuite/synth/issue1318/ram1.v b/testsuite/synth/issue1318/ram1.v new file mode 100644 index 000000000..a5939c0e2 --- /dev/null +++ b/testsuite/synth/issue1318/ram1.v @@ -0,0 +1,10 @@ +(* RAM_STYLE="BLOCK" *) +reg [7:0] lineMem [0:31]; + +reg [15:0] column_data = 0; +reg [ADDR_BITS - 1:0] line_mem_read_address = 0; + +always @(posedge clk) begin + column_data[7:0] <= lineMem[line_mem_read_address]; + column_data[15:8] <= data_in; +end |