testsuite/synth: add test for #1253

3 files changed, 58 insertions, 0 deletions

diff --git a/testsuite/synth/issue1253/repro1.vhdl b/testsuite/synth/issue1253/repro1.vhdl
new file mode 100644
index 000000000..d6d951062
--- /dev/null
+++ b/testsuite/synth/issue1253/repro1.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity repro1 is
+    port(C, CLR : in std_logic;
+         Q : out std_logic_vector(3 downto 0));
+end repro1;
+
+architecture archi of repro1 is
+    signal tmp: std_logic_vector(3 downto 0);
+begin
+    process (C, CLR)
+    begin
+        if (CLR='1') then
+            tmp <= "0000";
+        elsif (C'event and C='1') then
+            tmp <= std_logic_vector'(1 + signed(tmp));
+        end if;
+    end process;
+
+    Q <= tmp;
+
+end archi;
diff --git a/testsuite/synth/issue1253/repro2.vhdl b/testsuite/synth/issue1253/repro2.vhdl
new file mode 100644
index 000000000..cfeb59c78
--- /dev/null
+++ b/testsuite/synth/issue1253/repro2.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity repro1 is
+    port(C, CLR : in std_logic;
+         Q : out std_logic_vector(3 downto 0));
+end repro1;
+
+architecture archi of repro1 is
+    signal tmp: signed(3 downto 0);
+begin
+    process (C, CLR)
+    begin
+        if (CLR='1') then
+            tmp <= "0000";
+        elsif (C'event and C='1') then
+            tmp <= 1 + tmp;
+        end if;
+    end process;
+
+    Q <= std_logic_vector(tmp);
+
+end archi;
diff --git a/testsuite/synth/issue1253/testsuite.sh b/testsuite/synth/issue1253/testsuite.sh
new file mode 100755
index 000000000..a895b4b2f
--- /dev/null
+++ b/testsuite/synth/issue1253/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=-fsynopsys
+synth repro1.vhdl -e > syn_repro1.vhdl
+synth repro2.vhdl -e > syn_repro2.vhdl
+clean
+
+echo "Test successful"