testsuite/synth: add test for #1219

3 files changed, 84 insertions, 0 deletions

diff --git a/testsuite/synth/issue1219/tb_top.vhdl b/testsuite/synth/issue1219/tb_top.vhdl
new file mode 100644
index 000000000..9122d908f
--- /dev/null
+++ b/testsuite/synth/issue1219/tb_top.vhdl
@@ -0,0 +1,36 @@
+entity tb_top is
+end tb_top;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_top is
+  signal clk : std_logic;
+  signal addr : std_logic_vector (1 downto 0);
+  signal data : std_logic_vector (2 downto 0);
+begin
+  dut: entity work.top
+    port map (clk, addr, data);
+
+  process
+    procedure pulse is
+    begin
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+      clk <= '0';
+    end pulse;
+  begin
+    clk <= '0';
+
+    addr <= "00";
+    pulse;
+    assert data = "001" severity failure;
+    
+    addr <= "10";
+    pulse;
+    assert data = "100" severity failure;
+    
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1219/testsuite.sh b/testsuite/synth/issue1219/testsuite.sh
new file mode 100755
index 000000000..60399a753
--- /dev/null
+++ b/testsuite/synth/issue1219/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb top
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1219/top.vhdl b/testsuite/synth/issue1219/top.vhdl
new file mode 100644
index 000000000..905a3d191
--- /dev/null
+++ b/testsuite/synth/issue1219/top.vhdl
@@ -0,0 +1,41 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity top is
+	port(
+		clock : in std_logic;
+		addr : in std_logic_vector(1 downto 0);
+		data : out std_logic_vector(2 downto 0)
+	);
+end entity;
+
+architecture arch of top is
+
+	type rom_t is array(0 to 15) of std_logic_vector(3 downto 0);
+	constant rom : rom_t := (
+		"0001",
+		"0010",
+		"0100",
+		"1000",
+		"0001",
+		"0010",
+		"0100",
+		"1000",
+		"0001",
+		"0010",
+		"0100",
+		"1000",
+		"0001",
+		"0010",
+		"0100",
+		"1000"
+	);
+begin
+	process (clock)
+	begin
+		if rising_edge(clock) then
+			data <= rom(to_integer(unsigned(addr)))(2 downto 0);
+		end if;
+	end process;
+end architecture;