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author | Tristan Gingold <tgingold@free.fr> | 2020-04-13 07:08:43 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-13 07:08:43 +0200 |
commit | 5942e39d7768e432fb7394c66b11fdbd092ae78e (patch) | |
tree | e505450affb44dba8011966f3c0c1620aea52763 /testsuite/synth/issue1218 | |
parent | 5ed51a3a905c0096930c2b1c66932df24468dba9 (diff) | |
download | ghdl-5942e39d7768e432fb7394c66b11fdbd092ae78e.tar.gz ghdl-5942e39d7768e432fb7394c66b11fdbd092ae78e.tar.bz2 ghdl-5942e39d7768e432fb7394c66b11fdbd092ae78e.zip |
testsuite/synth: add a test for #1218
Diffstat (limited to 'testsuite/synth/issue1218')
-rw-r--r-- | testsuite/synth/issue1218/tb_top.vhdl | 41 | ||||
-rwxr-xr-x | testsuite/synth/issue1218/testsuite.sh | 8 | ||||
-rw-r--r-- | testsuite/synth/issue1218/top.vhdl | 16 |
3 files changed, 65 insertions, 0 deletions
diff --git a/testsuite/synth/issue1218/tb_top.vhdl b/testsuite/synth/issue1218/tb_top.vhdl new file mode 100644 index 000000000..590913c9b --- /dev/null +++ b/testsuite/synth/issue1218/tb_top.vhdl @@ -0,0 +1,41 @@ +entity tb_top is +end tb_top; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_top is + signal ch : integer range 0 to 7; + signal din : unsigned(7 downto 0); + signal dout : unsigned(7 downto 0); +begin + dut: entity work.top + port map (ch, din, dout); + + process + begin + report "test shift by 0 + 1"; + + ch <= 0; + din <= x"e7"; + wait for 1 ns; + assert dout = x"73" severity failure; + + report "test shift by 3 + 1"; + + ch <= 3; + din <= x"7e"; + wait for 1 ns; + assert dout = x"07" severity failure; + + report "test shift by 7 + 1"; + + ch <= 7; + din <= x"9b"; + wait for 1 ns; + assert dout = x"00" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1218/testsuite.sh b/testsuite/synth/issue1218/testsuite.sh new file mode 100755 index 000000000..88de793a8 --- /dev/null +++ b/testsuite/synth/issue1218/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_analyze top +clean + +echo "Test successful" diff --git a/testsuite/synth/issue1218/top.vhdl b/testsuite/synth/issue1218/top.vhdl new file mode 100644 index 000000000..b9169a28f --- /dev/null +++ b/testsuite/synth/issue1218/top.vhdl @@ -0,0 +1,16 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity top is +port ( + ch : in integer range 0 to 7; + din : in unsigned(7 downto 0); + dout : out unsigned(7 downto 0) +); +end entity; + +architecture arch of top is +begin + dout <= din srl (ch + 1); +end architecture; |