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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-09 22:04:30 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-09 22:04:30 +0200 |
| commit | 7bb42dba484fcbec66a97f613fa07a0299320443 (patch) | |
| tree | b6d2833a218aab1d0e535b65a215cf961ffe8d72 /testsuite/synth/issue1181 | |
| parent | d0af178e8f4a5387303727630a9a0690a1627ada (diff) | |
| download | ghdl-7bb42dba484fcbec66a97f613fa07a0299320443.tar.gz ghdl-7bb42dba484fcbec66a97f613fa07a0299320443.tar.bz2 ghdl-7bb42dba484fcbec66a97f613fa07a0299320443.zip | |
testsuite/synth: add a case for #1181
Diffstat (limited to 'testsuite/synth/issue1181')
| -rw-r--r-- | testsuite/synth/issue1181/bug.vhdl | 22 | ||||
| -rwxr-xr-x | testsuite/synth/issue1181/testsuite.sh | 9 |
2 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/synth/issue1181/bug.vhdl b/testsuite/synth/issue1181/bug.vhdl new file mode 100644 index 000000000..39a943d08 --- /dev/null +++ b/testsuite/synth/issue1181/bug.vhdl @@ -0,0 +1,22 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is + port( + dummy : in std_ulogic + ); +end bug; + +architecture behav of bug is +begin + process(all) + variable index : integer; + begin + index := 10; + if index > 3 then + -- index := index-1; + end if; + end process; + +end architecture; diff --git a/testsuite/synth/issue1181/testsuite.sh b/testsuite/synth/issue1181/testsuite.sh new file mode 100755 index 000000000..4c4a4df76 --- /dev/null +++ b/testsuite/synth/issue1181/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_analyze bug +clean + +echo "Test successful" |