testsuite/synth: add test for #1180

2 files changed, 41 insertions, 0 deletions

diff --git a/testsuite/synth/issue1180/bug.vhdl b/testsuite/synth/issue1180/bug.vhdl
new file mode 100644
index 000000000..6269ae385
--- /dev/null
+++ b/testsuite/synth/issue1180/bug.vhdl
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+	generic(
+		C_HIGH : natural := 5
+	);
+	port(
+		reset_n : in std_ulogic;
+		clk     : in std_ulogic;
+                res     : out natural
+	);
+end bug;
+
+architecture behav of bug is
+	subtype st is natural range 0 to C_HIGH;
+	signal c : st;
+begin
+	process(clk, reset_n)
+	begin
+		if reset_n = '0' then
+			c <= st'low;
+		elsif rising_edge(clk) then
+			if c = st'high then
+				c <= st'low;
+			else
+				c <= c + 1;
+			end if;
+		end if;
+	end process;
+        res <= c;
+end architecture;
diff --git a/testsuite/synth/issue1180/testsuite.sh b/testsuite/synth/issue1180/testsuite.sh
new file mode 100755
index 000000000..121ca9a6a
--- /dev/null
+++ b/testsuite/synth/issue1180/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze bug
+clean
+
+echo "Test successful"