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author | Tristan Gingold <tgingold@free.fr> | 2020-03-23 06:50:05 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-23 06:50:05 +0100 |
commit | 406323c01cd9263016a118106ea5a7c8e9cbe8ae (patch) | |
tree | 41c1a64549f4fe0cdcb6a68a8230fa1838b1c9a1 /testsuite/synth/issue1166/tb_ent.vhdl | |
parent | e1e293701bb457af7bffc2e18a890cf552599144 (diff) | |
download | ghdl-406323c01cd9263016a118106ea5a7c8e9cbe8ae.tar.gz ghdl-406323c01cd9263016a118106ea5a7c8e9cbe8ae.tar.bz2 ghdl-406323c01cd9263016a118106ea5a7c8e9cbe8ae.zip |
testsuite/synth: add a test for #1166
Diffstat (limited to 'testsuite/synth/issue1166/tb_ent.vhdl')
-rw-r--r-- | testsuite/synth/issue1166/tb_ent.vhdl | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/testsuite/synth/issue1166/tb_ent.vhdl b/testsuite/synth/issue1166/tb_ent.vhdl new file mode 100644 index 000000000..016f6b685 --- /dev/null +++ b/testsuite/synth/issue1166/tb_ent.vhdl @@ -0,0 +1,45 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tb_ent is +end; + +architecture a of tb_ent is + signal a, enable, d_in, d_out : std_logic; +begin + uut: entity work.ent + port map ( + a => a, + enable => enable, + d_in => d_in, + d_out => d_out + ); + + process + begin + a <= '0'; + enable <= '0'; + + wait for 10 ns; + assert d_out = '0'; + + a <= '1'; + + wait for 10 ns; + assert d_out = '1' severity failure; + + enable <= '1'; + a <= 'Z'; + d_in <= '0'; + + wait for 10 ns; + assert a = '0' severity failure; + + d_in <= '1'; + + wait for 10 ns; + assert a = '1' severity failure; + + wait; + end process; +end; |