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authorTristan Gingold <tgingold@free.fr>2020-03-23 06:50:05 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-23 06:50:05 +0100
commit406323c01cd9263016a118106ea5a7c8e9cbe8ae (patch)
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testsuite/synth: add a test for #1166
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diff --git a/testsuite/synth/issue1166/ent.vhdl b/testsuite/synth/issue1166/ent.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+ port (
+ a : inout std_logic;
+ enable : in std_logic;
+ d_in : in std_logic;
+ d_out : out std_logic
+ );
+end;
+
+architecture a of ent is
+begin
+ process(all)
+ begin
+ if enable then
+ a <= d_in;
+ else
+ a <= 'Z';
+ end if;
+ end process;
+ d_out <= a;
+end;