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author | Tristan Gingold <tgingold@free.fr> | 2020-03-23 06:50:05 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-23 06:50:05 +0100 |
commit | 406323c01cd9263016a118106ea5a7c8e9cbe8ae (patch) | |
tree | 41c1a64549f4fe0cdcb6a68a8230fa1838b1c9a1 /testsuite/synth/issue1166/ent.vhdl | |
parent | e1e293701bb457af7bffc2e18a890cf552599144 (diff) | |
download | ghdl-406323c01cd9263016a118106ea5a7c8e9cbe8ae.tar.gz ghdl-406323c01cd9263016a118106ea5a7c8e9cbe8ae.tar.bz2 ghdl-406323c01cd9263016a118106ea5a7c8e9cbe8ae.zip |
testsuite/synth: add a test for #1166
Diffstat (limited to 'testsuite/synth/issue1166/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue1166/ent.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/issue1166/ent.vhdl b/testsuite/synth/issue1166/ent.vhdl new file mode 100644 index 000000000..8f2f1b514 --- /dev/null +++ b/testsuite/synth/issue1166/ent.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + a : inout std_logic; + enable : in std_logic; + d_in : in std_logic; + d_out : out std_logic + ); +end; + +architecture a of ent is +begin + process(all) + begin + if enable then + a <= d_in; + else + a <= 'Z'; + end if; + end process; + d_out <= a; +end; |