testsuite/synth: add test for #1133

1 files changed, 24 insertions, 0 deletions

diff --git a/testsuite/synth/issue1133/foo.vhdl b/testsuite/synth/issue1133/foo.vhdl
new file mode 100644
index 000000000..32a972cda
--- /dev/null
+++ b/testsuite/synth/issue1133/foo.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity foo is
+  port (
+    input        : in std_logic_vector(7 downto 0);
+    output_ok    : out std_logic_vector(7 downto 0);
+    output_error : out std_logic_vector(7 downto 0)
+  );
+end foo;
+
+architecture foo of foo is
+
+  signal null_vector : std_logic_vector(-1 downto 0) := (others => '0');
+
+begin
+
+  -- This works fine
+  null_vector  <= input(null_vector'range);
+  output_ok    <= null_vector & (7 downto 0 => '0');
+  -- This doesn't
+  output_error <= input(-1 downto 0) & (7 downto 0 => '0');
+
+end foo;