testsuite/synth: add test for #1080

4 files changed, 105 insertions, 1 deletions

diff --git a/testsuite/synth/issue1080/repro3.vhdl b/testsuite/synth/issue1080/repro3.vhdl
new file mode 100644
index 000000000..252f705c8
--- /dev/null
+++ b/testsuite/synth/issue1080/repro3.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity repro3 is
+  port (
+    clk : std_logic;
+    led : out std_logic);
+end;
+
+architecture behav of repro3 is
+    constant LOOKUP_LEN   : integer := 6;
+    constant LOOKUP_TABLE : unsigned(LOOKUP_LEN*8-1 downto 0) :=
+        x"010205" & x"060708";
+
+    signal brt : unsigned(7 downto 0) := (others => '0');
+
+begin
+  led <= brt (0);
+    lookup_p : process(Clk)
+        variable idx : integer range 0 to LOOKUP_LEN-1 := LOOKUP_LEN-1;
+    begin
+        if rising_edge(Clk) then
+            brt <= lookup_table(8*idx+7 downto 8*idx);
+
+            if idx /= 0 then
+              idx := idx - 1;
+            else
+              idx := LOOKUP_LEN-1;
+            end if;
+        end if;
+    end process;
+end behav;
diff --git a/testsuite/synth/issue1080/repro3_1.vhdl b/testsuite/synth/issue1080/repro3_1.vhdl
new file mode 100644
index 000000000..6a21d0f4c
--- /dev/null
+++ b/testsuite/synth/issue1080/repro3_1.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro3_1 is
+  port (
+    clk : std_logic;
+    led : out std_logic_vector(7 downto 0));
+end;
+
+architecture behav of repro3_1 is
+    constant LOOKUP_LEN   : integer := 6;
+    constant LOOKUP_TABLE : std_logic_vector(LOOKUP_LEN*8-1 downto 0) :=
+      x"010205" & x"060708";
+    -- x"010205060708";
+    --  -> const_bit (0x5060708, 0x102)
+begin
+    lookup_p : process(Clk)
+        variable idx : integer range 0 to LOOKUP_LEN-1 := LOOKUP_LEN-1;
+    begin
+        if rising_edge(Clk) then
+          led <= lookup_table(8*idx+7 downto 8*idx);
+
+            if idx /= 0 then
+              idx := idx - 1;
+            else
+              idx := LOOKUP_LEN-1;
+            end if;
+        end if;
+    end process;
+end behav;
diff --git a/testsuite/synth/issue1080/tb_repro3_1.vhdl b/testsuite/synth/issue1080/tb_repro3_1.vhdl
new file mode 100644
index 000000000..229dcf17c
--- /dev/null
+++ b/testsuite/synth/issue1080/tb_repro3_1.vhdl
@@ -0,0 +1,30 @@
+entity tb_repro3_1 is
+end tb_repro3_1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_repro3_1 is
+  signal clk : std_logic;
+  signal led : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.repro3_1
+    port map (clk, led);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    pulse;
+    assert led = x"01" severity failure;
+
+    pulse;
+    assert led = x"02" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1080/testsuite.sh b/testsuite/synth/issue1080/testsuite.sh
index 24843415d..edb7da40a 100755
--- a/testsuite/synth/issue1080/testsuite.sh
+++ b/testsuite/synth/issue1080/testsuite.sh
@@ -2,10 +2,21 @@
 
 . ../../testenv.sh
 
-for t in repro repro2 repro2_1; do
+for t in repro repro2 repro2_1 repro3; do
     synth $t.vhdl -e $t > syn_$t.vhdl
     analyze syn_$t.vhdl
     clean
 done
 
+for t in repro3_1; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
 echo "Test successful"