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authorTristan Gingold <tgingold@free.fr>2020-01-02 10:04:58 +0100
committerTristan Gingold <tgingold@free.fr>2020-01-02 10:04:58 +0100
commit46f881b0ad6a674bdb92ca8549ac71f4b8f9b6a4 (patch)
tree1725b07d0aaff46d008506c2a2d6b2aea8f05a69 /testsuite/synth/issue1064
parentd56c58668b10ca7a6684cb518b4978207c7b88b2 (diff)
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testsuite/synth: add a test for #1064
Diffstat (limited to 'testsuite/synth/issue1064')
-rw-r--r--testsuite/synth/issue1064/tb_test.vhdl20
-rw-r--r--testsuite/synth/issue1064/test.vhdl23
-rwxr-xr-xtestsuite/synth/issue1064/testsuite.sh17
3 files changed, 60 insertions, 0 deletions
diff --git a/testsuite/synth/issue1064/tb_test.vhdl b/testsuite/synth/issue1064/tb_test.vhdl
new file mode 100644
index 000000000..1910605df
--- /dev/null
+++ b/testsuite/synth/issue1064/tb_test.vhdl
@@ -0,0 +1,20 @@
+entity tb_test is
+end tb_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test is
+ signal a : std_logic;
+ signal b : std_logic;
+begin
+ dut: entity work.test
+ port map (a, b);
+
+ process
+ begin
+ wait for 1 ns;
+ assert b = '0' severity failure;
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1064/test.vhdl b/testsuite/synth/issue1064/test.vhdl
new file mode 100644
index 000000000..7895a602c
--- /dev/null
+++ b/testsuite/synth/issue1064/test.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test is
+ port (i : std_ulogic;
+ o : out std_ulogic);
+end entity test;
+
+architecture behaviour of test is
+ procedure zot(e: inout std_ulogic) is
+ begin
+ e := '0';
+ end;
+
+begin
+ execute1_1: process(all)
+ variable blah: std_ulogic;
+ begin
+ blah := i;
+ zot(blah);
+ o <= blah;
+ end process;
+end architecture behaviour;
diff --git a/testsuite/synth/issue1064/testsuite.sh b/testsuite/synth/issue1064/testsuite.sh
new file mode 100755
index 000000000..ffd46daf3
--- /dev/null
+++ b/testsuite/synth/issue1064/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in test; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t --ieee-asserts=disable-at-0
+ clean
+done
+
+echo "Test successful"