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author | Tristan Gingold <tgingold@free.fr> | 2019-11-23 18:04:28 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-23 18:04:28 +0100 |
commit | 185e18dbf9d1c78eafc13c4824c8eab2fd686e12 (patch) | |
tree | d0105f8554e003f5631cde293c2e49c9e65ea53d /testsuite/synth/issue1025/tb_ent.vhdl | |
parent | c1e2a5e5cad68c90f47ba0bc05f2285b3ca584d0 (diff) | |
download | ghdl-185e18dbf9d1c78eafc13c4824c8eab2fd686e12.tar.gz ghdl-185e18dbf9d1c78eafc13c4824c8eab2fd686e12.tar.bz2 ghdl-185e18dbf9d1c78eafc13c4824c8eab2fd686e12.zip |
testsuite/synth: add testcase for #1025
Diffstat (limited to 'testsuite/synth/issue1025/tb_ent.vhdl')
-rw-r--r-- | testsuite/synth/issue1025/tb_ent.vhdl | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/issue1025/tb_ent.vhdl b/testsuite/synth/issue1025/tb_ent.vhdl new file mode 100644 index 000000000..30ead5166 --- /dev/null +++ b/testsuite/synth/issue1025/tb_ent.vhdl @@ -0,0 +1,39 @@ +entity tb_ent is +end tb_ent; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ent is + signal clk : std_logic; + signal counter : natural; + signal rst : std_logic; +begin + dut: entity work.ent + port map ( + rst => rst, + clk => clk, + counter => counter); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + rst <= '1'; + pulse; + assert counter = 0 severity failure; + rst <= '0'; + pulse; + assert counter = 1 severity failure; + pulse; + assert counter = 2 severity failure; + pulse; + assert counter = 3 severity failure; + wait; + end process; +end behav; |