testsuite/synth: add testcase for previous commit.

3 files changed, 58 insertions, 1 deletions

diff --git a/testsuite/synth/iassoc01/iassoc11.vhdl b/testsuite/synth/iassoc01/iassoc11.vhdl
new file mode 100644
index 000000000..f66c0ef59
--- /dev/null
+++ b/testsuite/synth/iassoc01/iassoc11.vhdl
@@ -0,0 +1,28 @@
+use work.pkg.all;
+
+entity riassoc11 is
+  port (v : nat_rec;
+        res : out natural);
+end riassoc11;
+
+architecture behav of riassoc11 is
+begin
+  res <= v.a + v.b;
+end behav;
+
+entity iassoc11 is
+  port (a, b : natural;
+        res : out natural);
+end iassoc11;
+
+use work.pkg.all;
+
+architecture behav of iassoc11 is
+  component riassoc11 is
+    port (v : nat_rec;
+          res : out natural);
+  end component;
+begin
+  inst : riassoc11
+    port map (v.a => a, v.b => b, res => res);
+end behav;
diff --git a/testsuite/synth/iassoc01/tb_iassoc11.vhdl b/testsuite/synth/iassoc01/tb_iassoc11.vhdl
new file mode 100644
index 000000000..e8bb36289
--- /dev/null
+++ b/testsuite/synth/iassoc01/tb_iassoc11.vhdl
@@ -0,0 +1,29 @@
+entity tb_iassoc11 is
+end tb_iassoc11;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_iassoc11 is
+  signal a : natural;
+  signal b : natural;
+  signal res : natural;
+begin
+  dut: entity work.iassoc11
+    port map (a, b, res);
+
+  process
+  begin
+    a <= 1;
+    b <= 5;
+    wait for 1 ns;
+    assert res = 6 severity failure;
+
+    a <= 197;
+    b <= 203;
+    wait for 1 ns;
+    assert res = 400 severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/iassoc01/testsuite.sh b/testsuite/synth/iassoc01/testsuite.sh
index b1ed1293f..d00af5014 100755
--- a/testsuite/synth/iassoc01/testsuite.sh
+++ b/testsuite/synth/iassoc01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in iassoc01 iassoc02 iassoc03 iassoc04; do
+for t in iassoc01 iassoc02 iassoc03 iassoc04 iassoc11; do
     analyze pkg.vhdl $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean