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authorTristan Gingold <tgingold@free.fr>2019-09-13 07:28:55 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-13 07:28:55 +0200
commit32fee63a7b9d7fd5b86c1efc7280441e7d0dbf1f (patch)
treea776901d4525e7120732e0bf688036de5381837c /testsuite/synth/func01/tb_func05.vhdl
parent2e61401a3d12ede4bb72bc6749d7f6ae905d6376 (diff)
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testsuite/synth: add more tests in func01.
Diffstat (limited to 'testsuite/synth/func01/tb_func05.vhdl')
-rw-r--r--testsuite/synth/func01/tb_func05.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/func01/tb_func05.vhdl b/testsuite/synth/func01/tb_func05.vhdl
new file mode 100644
index 000000000..8f2e11704
--- /dev/null
+++ b/testsuite/synth/func01/tb_func05.vhdl
@@ -0,0 +1,26 @@
+entity tb_func05 is
+end tb_func05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func05 is
+ signal r : std_logic_vector(15 downto 0);
+ signal s : natural;
+begin
+ dut: entity work.func05
+ port map (s, r);
+
+ process
+ begin
+ s <= 2;
+ wait for 1 ns;
+ assert r = x"1234" severity failure;
+
+ s <= 3;
+ wait for 1 ns;
+ assert r = x"0000" severity failure;
+
+ wait;
+ end process;
+end behav;