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author | Tristan Gingold <tgingold@free.fr> | 2019-09-23 06:49:49 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-23 06:49:49 +0200 |
commit | 6558eaedc8fa11346b251fa197a286da74e656e0 (patch) | |
tree | 691e4968bb1c40fa979da229eb3ef4bf3a2e1eca /testsuite/synth/func01/func08.vhdl | |
parent | b088e95b6964ef70a2856bf19b33112d391d8aa5 (diff) | |
download | ghdl-6558eaedc8fa11346b251fa197a286da74e656e0.tar.gz ghdl-6558eaedc8fa11346b251fa197a286da74e656e0.tar.bz2 ghdl-6558eaedc8fa11346b251fa197a286da74e656e0.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/func01/func08.vhdl')
-rw-r--r-- | testsuite/synth/func01/func08.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/func01/func08.vhdl b/testsuite/synth/func01/func08.vhdl new file mode 100644 index 000000000..d8f0e4d18 --- /dev/null +++ b/testsuite/synth/func01/func08.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity func08 is + port (v : std_ulogic_vector (31 downto 0); + r : out integer); +end func08; + +architecture behav of func08 is + function fls (val: std_ulogic_vector(31 downto 0)) return integer is + variable ret: integer; + begin + ret := 32; + for i in val'range loop + if val(i) = '1' then + ret := 31 - i; + exit; + end if; + end loop; + + return ret; + end; +begin + r <= fls(v); +end behav; |