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authorTristan Gingold <tgingold@free.fr>2019-06-30 13:46:08 +0200
committerTristan Gingold <tgingold@free.fr>2019-06-30 13:46:08 +0200
commit181165f90d7ab05cff1c2bc5894d0143f03d3634 (patch)
treebb27972df2886504ba7b9d426b39c4840c2a077a /testsuite/synth/fsm01/tb_fsm_2s.vhdl
parent10b2f5a4012ae368dfcf49628281e34674f913d7 (diff)
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testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/fsm01/tb_fsm_2s.vhdl')
-rw-r--r--testsuite/synth/fsm01/tb_fsm_2s.vhdl44
1 files changed, 44 insertions, 0 deletions
diff --git a/testsuite/synth/fsm01/tb_fsm_2s.vhdl b/testsuite/synth/fsm01/tb_fsm_2s.vhdl
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+++ b/testsuite/synth/fsm01/tb_fsm_2s.vhdl
@@ -0,0 +1,44 @@
+entity tb_fsm_2s is
+end tb_fsm_2s;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_fsm_2s is
+ signal clk : std_logic;
+ signal rst : std_logic;
+ signal din : std_logic;
+ signal done : std_logic;
+begin
+ dut: entity work.fsm_2s
+ port map (
+ done => done,
+ d => din,
+ clk => clk,
+ rst => rst);
+
+ process
+ constant dat : std_logic_vector := b"10010";
+ constant res : std_logic_vector := b"01001";
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ rst <= '1';
+ din <= '0';
+ pulse;
+ assert done = '0' severity failure;
+ -- Test the whole sequence.
+ rst <= '0';
+ for i in dat'range loop
+ din <= dat (i);
+ pulse;
+ assert done = res(i) severity failure;
+ end loop;
+ wait;
+ end process;
+end behav;