testsuite/synyh: add a test for exit statement.

5 files changed, 154 insertions, 0 deletions

diff --git a/testsuite/synth/exit01/exit01.vhdl b/testsuite/synth/exit01/exit01.vhdl
new file mode 100644
index 000000000..cc97c217d
--- /dev/null
+++ b/testsuite/synth/exit01/exit01.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity exit01 is
+  port (val : std_logic_vector (3 downto 0);
+        res : out integer);
+end exit01;
+
+architecture behav of exit01 is
+begin
+  process(val)
+  begin
+    res <= 4;
+    for i in val'reverse_range loop
+      if val (i) = '1' then
+        res <= i;
+        exit;
+      end if;
+    end loop;
+  end process;
+end behav;
diff --git a/testsuite/synth/exit01/exit02.vhdl b/testsuite/synth/exit01/exit02.vhdl
new file mode 100644
index 000000000..17895dce9
--- /dev/null
+++ b/testsuite/synth/exit01/exit02.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity exit02 is
+  port (val : std_logic_vector (3 downto 0);
+        res : out integer);
+end exit02;
+
+architecture behav of exit02 is
+  function ffs (v : std_logic_vector (3 downto 0)) return natural
+  is
+    variable r : natural;
+  begin
+    r := 4;
+    for i in v'reverse_range loop
+      if v (i) = '1' then
+        r := i;
+        exit;
+      end if;
+    end loop;
+    return r;
+  end ffs;
+begin
+  res <= ffs (val);
+end behav;
diff --git a/testsuite/synth/exit01/tb_exit01.vhdl b/testsuite/synth/exit01/tb_exit01.vhdl
new file mode 100644
index 000000000..6d184cae1
--- /dev/null
+++ b/testsuite/synth/exit01/tb_exit01.vhdl
@@ -0,0 +1,46 @@
+entity tb_exit01 is
+end tb_exit01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_exit01 is
+  signal v : std_logic_vector(3 downto 0);
+  signal r : integer;
+begin
+  dut: entity work.exit01
+    port map (val => v, res => r);
+
+  process
+  begin
+    v <= "0001";
+    wait for 1 ns;
+    assert r = 0 severity failure;
+
+    v <= "0010";
+    wait for 1 ns;
+    assert r = 1 severity failure;
+
+    v <= "0100";
+    wait for 1 ns;
+    assert r = 2 severity failure;
+
+    v <= "1000";
+    wait for 1 ns;
+    assert r = 3 severity failure;
+
+    v <= "0000";
+    wait for 1 ns;
+    assert r = 4 severity failure;
+
+    v <= "0110";
+    wait for 1 ns;
+    assert r = 1 severity failure;
+
+    v <= "1001";
+    wait for 1 ns;
+    assert r = 0 severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/exit01/tb_exit02.vhdl b/testsuite/synth/exit01/tb_exit02.vhdl
new file mode 100644
index 000000000..47a53bab9
--- /dev/null
+++ b/testsuite/synth/exit01/tb_exit02.vhdl
@@ -0,0 +1,46 @@
+entity tb_exit02 is
+end tb_exit02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_exit02 is
+  signal v : std_logic_vector(3 downto 0);
+  signal r : integer;
+begin
+  dut: entity work.exit02
+    port map (val => v, res => r);
+
+  process
+  begin
+    v <= "0001";
+    wait for 1 ns;
+    assert r = 0 severity failure;
+
+    v <= "0010";
+    wait for 1 ns;
+    assert r = 1 severity failure;
+
+    v <= "0100";
+    wait for 1 ns;
+    assert r = 2 severity failure;
+
+    v <= "1000";
+    wait for 1 ns;
+    assert r = 3 severity failure;
+
+    v <= "0000";
+    wait for 1 ns;
+    assert r = 4 severity failure;
+
+    v <= "0110";
+    wait for 1 ns;
+    assert r = 1 severity failure;
+
+    v <= "1001";
+    wait for 1 ns;
+    assert r = 0 severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/exit01/testsuite.sh b/testsuite/synth/exit01/testsuite.sh
new file mode 100755
index 000000000..a8a8026f7
--- /dev/null
+++ b/testsuite/synth/exit01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in exit01 exit02; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"