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authorTristan Gingold <tgingold@free.fr>2019-09-04 06:52:02 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-04 06:52:02 +0200
commit95433bc986b16badf5a48ab00df861d0424ca983 (patch)
treed63a2bb74ee44cbefc814ddae9276f06f464dac8 /testsuite/synth/dispout01/tb_rec06.vhdl
parentfcaac98cefe3917610b88de7cc776a9fe2ee10a3 (diff)
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testsuite/synth: add tests for previous commit.
Diffstat (limited to 'testsuite/synth/dispout01/tb_rec06.vhdl')
-rw-r--r--testsuite/synth/dispout01/tb_rec06.vhdl27
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/dispout01/tb_rec06.vhdl b/testsuite/synth/dispout01/tb_rec06.vhdl
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+entity tb_rec06 is
+end tb_rec06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec06_pkg.all;
+
+architecture behav of tb_rec06 is
+ signal inp : std_logic;
+ signal r : myrec;
+begin
+ dut: entity work.rec06
+ port map (inp => inp, o => r);
+
+ process
+ begin
+ inp <= '1';
+ wait for 1 ns;
+ assert r = (a => (c => 2, d => "1000"), b => '0') severity failure;
+
+ inp <= '0';
+ wait for 1 ns;
+ assert r = (a => (c => 3, d => "0000"), b => '1') severity failure;
+
+ wait;
+ end process;
+end behav;