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author | Tristan Gingold <tgingold@free.fr> | 2020-05-03 16:57:41 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-04 19:04:08 +0200 |
commit | d7f364c707c2767743150d92eff0fab3ddd58ceb (patch) | |
tree | aba70094e890fca53d0c6641e077dfbb936967b8 /testsuite/synth/case02/tb_case03.vhdl | |
parent | 3629ed753e2a432d100b54bc94473ada803dc43c (diff) | |
download | ghdl-d7f364c707c2767743150d92eff0fab3ddd58ceb.tar.gz ghdl-d7f364c707c2767743150d92eff0fab3ddd58ceb.tar.bz2 ghdl-d7f364c707c2767743150d92eff0fab3ddd58ceb.zip |
testsuite/synth: add a test for previous commits.
Diffstat (limited to 'testsuite/synth/case02/tb_case03.vhdl')
-rw-r--r-- | testsuite/synth/case02/tb_case03.vhdl | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/testsuite/synth/case02/tb_case03.vhdl b/testsuite/synth/case02/tb_case03.vhdl new file mode 100644 index 000000000..6988b1ca1 --- /dev/null +++ b/testsuite/synth/case02/tb_case03.vhdl @@ -0,0 +1,46 @@ +entity tb_case03 is +end tb_case03; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_case03 is + signal clk : std_logic; + signal opc : std_logic_vector (2 downto 0); + signal arg : std_logic_vector (7 downto 0); + signal res : std_logic_vector (7 downto 0); + signal par : std_logic; +begin + dut: entity work.case03 + port map (clk, opc, arg, res, par); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + opc <= "000"; + arg <= x"45"; + pulse; + assert res = x"ba" severity failure; + assert par = '1' severity failure; + + opc <= "010"; + arg <= x"55"; + pulse; + assert res = x"aa" severity failure; + assert par = '0' severity failure; + + opc <= "110"; + arg <= x"57"; + pulse; + assert res = x"57" severity failure; + assert par = '0' severity failure; + + wait; + end process; +end behav; |