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author | Tristan Gingold <tgingold@free.fr> | 2019-09-07 08:44:46 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-07 08:44:46 +0200 |
commit | 34269470ff0d36c3b0b45a2daa9390bddabe2050 (patch) | |
tree | 33f492ca00a63731d2ee8201c8073b4af342f814 /testsuite/synth/case02/tb_case01.vhdl | |
parent | 70f258f0330faf7f6a9383c99078210ece55132a (diff) | |
download | ghdl-34269470ff0d36c3b0b45a2daa9390bddabe2050.tar.gz ghdl-34269470ff0d36c3b0b45a2daa9390bddabe2050.tar.bz2 ghdl-34269470ff0d36c3b0b45a2daa9390bddabe2050.zip |
testsuite/synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/case02/tb_case01.vhdl')
-rw-r--r-- | testsuite/synth/case02/tb_case01.vhdl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/synth/case02/tb_case01.vhdl b/testsuite/synth/case02/tb_case01.vhdl new file mode 100644 index 000000000..95b8561d8 --- /dev/null +++ b/testsuite/synth/case02/tb_case01.vhdl @@ -0,0 +1,32 @@ +entity tb_case01 is +end tb_case01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_case01 is + signal a : std_logic_vector (1 downto 0); + signal o : std_logic_vector (1 downto 0); + signal clk : std_logic; +begin + dut: entity work.case01 + port map (a, clk, o); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + a <= "00"; + pulse; + a <= "10"; + pulse; + assert o = "00" severity failure; + + wait; + end process; +end behav; |