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author | Tristan Gingold <tgingold@free.fr> | 2019-09-25 20:55:25 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-25 20:56:49 +0200 |
commit | 84d5da4e8a15bb049cecd08e26ecfca15d23f820 (patch) | |
tree | b8283b3c75fc369c099766582fffed8d6cdbf88f /testsuite/synth/case02/case02.vhdl | |
parent | 14c81512c7cce51e7781d527bd82be9ed5f34be3 (diff) | |
download | ghdl-84d5da4e8a15bb049cecd08e26ecfca15d23f820.tar.gz ghdl-84d5da4e8a15bb049cecd08e26ecfca15d23f820.tar.bz2 ghdl-84d5da4e8a15bb049cecd08e26ecfca15d23f820.zip |
testsuite/synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/case02/case02.vhdl')
-rw-r--r-- | testsuite/synth/case02/case02.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/case02/case02.vhdl b/testsuite/synth/case02/case02.vhdl new file mode 100644 index 000000000..6dba9d594 --- /dev/null +++ b/testsuite/synth/case02/case02.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity case02 is + port (a : std_logic_vector (1 downto 0); + o : out std_logic); +end case02; + +architecture behav of case02 is +begin + process (a) + begin + case a(1 downto 0) is + when "01" => + o <= '1'; + when others => + o <= '0'; + end case; + end process; +end behav; |