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author | Tristan Gingold <tgingold@free.fr> | 2019-09-07 08:44:46 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-07 08:44:46 +0200 |
commit | 34269470ff0d36c3b0b45a2daa9390bddabe2050 (patch) | |
tree | 33f492ca00a63731d2ee8201c8073b4af342f814 /testsuite/synth/case02/case01.vhdl | |
parent | 70f258f0330faf7f6a9383c99078210ece55132a (diff) | |
download | ghdl-34269470ff0d36c3b0b45a2daa9390bddabe2050.tar.gz ghdl-34269470ff0d36c3b0b45a2daa9390bddabe2050.tar.bz2 ghdl-34269470ff0d36c3b0b45a2daa9390bddabe2050.zip |
testsuite/synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/case02/case01.vhdl')
-rw-r--r-- | testsuite/synth/case02/case01.vhdl | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/case02/case01.vhdl b/testsuite/synth/case02/case01.vhdl new file mode 100644 index 000000000..702d7244c --- /dev/null +++ b/testsuite/synth/case02/case01.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity case01 is + port (a : std_logic_vector (1 downto 0); + clk : std_logic; + o : out std_logic_vector(1 downto 0)); +end case01; + +architecture behav of case01 is +begin + process (clk) + begin + if rising_edge (clk) then + case a is + when "01" => + o (0) <= '1'; + when "11" => + o (1) <= '1'; + when "00" => + o (0) <= '0'; + when "10" => + o (1) <= '0'; + when others => + o <= "00"; + end case; + end if; + end process; +end behav; |