diff options
author | Tristan Gingold <tgingold@free.fr> | 2020-05-15 05:40:15 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2020-05-15 05:40:15 +0200 |
commit | 84f0148e9e01c14993d5473e66a4ad6eee819798 (patch) | |
tree | d248b8c283beb327c1948780f83707c764c7b0ce /testsuite/synth/case01/case06.vhdl | |
parent | f4d0374404bc7539f78d07e0a926f9a600ff0096 (diff) | |
download | ghdl-84f0148e9e01c14993d5473e66a4ad6eee819798.tar.gz ghdl-84f0148e9e01c14993d5473e66a4ad6eee819798.tar.bz2 ghdl-84f0148e9e01c14993d5473e66a4ad6eee819798.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/case01/case06.vhdl')
-rw-r--r-- | testsuite/synth/case01/case06.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/case01/case06.vhdl b/testsuite/synth/case01/case06.vhdl new file mode 100644 index 000000000..f66569dbf --- /dev/null +++ b/testsuite/synth/case01/case06.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity case06 is + port ( + a : in std_logic; + b : out std_logic + ); +end entity; + +architecture a of case06 is +begin + process(a) + begin + case a is + when '0' => + b <= '0'; + when 'L' => + b <= '1'; + when others => + b <= 'Z'; + end case; + end process; +end architecture; |