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author | Tristan Gingold <tgingold@free.fr> | 2019-10-05 08:05:26 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-05 08:05:26 +0200 |
commit | 5c72f37c3eaf69d59f0f9a22473d68ce70858450 (patch) | |
tree | 280d1c32e362368808a31c62f3e90c9b4327fb09 /testsuite/synth/block01/block02.vhdl | |
parent | b574ebd8a8e74b45d2680366e2a3c478ee388a9c (diff) | |
download | ghdl-5c72f37c3eaf69d59f0f9a22473d68ce70858450.tar.gz ghdl-5c72f37c3eaf69d59f0f9a22473d68ce70858450.tar.bz2 ghdl-5c72f37c3eaf69d59f0f9a22473d68ce70858450.zip |
testsuite/synth: add a test for block declarations.
Diffstat (limited to 'testsuite/synth/block01/block02.vhdl')
-rw-r--r-- | testsuite/synth/block01/block02.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/block01/block02.vhdl b/testsuite/synth/block01/block02.vhdl new file mode 100644 index 000000000..a22edae17 --- /dev/null +++ b/testsuite/synth/block01/block02.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity block02 is + port (q : out std_logic; + d : std_logic; + clk : std_logic); +end block02; + +architecture behav of block02 is +begin + b1 : block + signal s : std_logic; + begin + process (clk) is + begin + if rising_edge (clk) then + s <= d; + end if; + end process; + + q <= s; + end block b1; +end behav; |