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authorTristan Gingold <tgingold@free.fr>2020-03-27 08:12:09 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-27 08:12:09 +0100
commit9552d531495d7d0313797de3f6c077fdbf24c028 (patch)
treeb35ee024076f5de325d8468eb0e01efce6ed73df /testsuite/synth/arr03
parent2ab3c5f0ee6756b29635b3583f4eec7155640058 (diff)
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testsuite/synth: add a test for multidim arrays.
Diffstat (limited to 'testsuite/synth/arr03')
-rw-r--r--testsuite/synth/arr03/mdim01.vhdl30
-rw-r--r--testsuite/synth/arr03/tb_mdim01.vhdl28
-rwxr-xr-xtestsuite/synth/arr03/testsuite.sh9
3 files changed, 67 insertions, 0 deletions
diff --git a/testsuite/synth/arr03/mdim01.vhdl b/testsuite/synth/arr03/mdim01.vhdl
new file mode 100644
index 000000000..1f1f733f7
--- /dev/null
+++ b/testsuite/synth/arr03/mdim01.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mdim01 is
+ port (a0, a1 : std_logic_vector (3 downto 0);
+ o0 : out std_logic_vector (3 downto 0));
+end mdim01;
+
+architecture behav of mdim01 is
+ type t_matrix is array (0 to 1, 3 downto 0) of boolean;
+ constant mat : t_matrix :=
+ (0 => (3 => true, 2 => true, 1 => false, 0 => false),
+ 1 => (3 => true, 2 => false, 1 => true, 0 => false));
+begin
+ process (a0, a1)
+ variable b : std_logic;
+ begin
+ for i in t_matrix'range(2) loop
+ if mat (0, i) then
+ b := a0 (i);
+ else
+ b := '0';
+ end if;
+ if mat (1, i) then
+ b := b xor a1 (i);
+ end if;
+ o0 (i) <= b;
+ end loop;
+ end process;
+end behav;
diff --git a/testsuite/synth/arr03/tb_mdim01.vhdl b/testsuite/synth/arr03/tb_mdim01.vhdl
new file mode 100644
index 000000000..6b54b32af
--- /dev/null
+++ b/testsuite/synth/arr03/tb_mdim01.vhdl
@@ -0,0 +1,28 @@
+entity tb_mdim01 is
+end tb_mdim01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_mdim01 is
+ signal a : std_logic_vector (3 downto 0);
+ signal b : std_logic_vector (3 downto 0);
+ signal c : std_logic_vector (3 downto 0);
+begin
+ dut: entity work.mdim01
+ port map (a, b, c);
+
+ process
+ constant av : std_logic_vector := b"1101";
+ constant bv : std_logic_vector := b"0111";
+ constant cv : std_logic_vector := b"0011";
+ constant zv : std_logic_vector := b"0111";
+ begin
+ a <= "1111";
+ b <= "0000";
+ wait for 1 ns;
+ assert c = "1100" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/arr03/testsuite.sh b/testsuite/synth/arr03/testsuite.sh
new file mode 100755
index 000000000..b00cba4a6
--- /dev/null
+++ b/testsuite/synth/arr03/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in mdim01; do
+ synth_tb $t
+done
+
+echo "Test successful"