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author | Tristan Gingold <tgingold@free.fr> | 2019-07-01 18:22:06 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-01 18:22:06 +0200 |
commit | fe35233c6f06c13a6a18db69da774a29a1993966 (patch) | |
tree | 37fe5abfcb6141f3268abcff1c0197c45985abdc /testsuite/synth/arr01/tb_arr04.vhdl | |
parent | 10e0d932d67e90263dfd393be8b3719e26fe6514 (diff) | |
download | ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.tar.gz ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.tar.bz2 ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.zip |
testsuite/synth: add arr01
Diffstat (limited to 'testsuite/synth/arr01/tb_arr04.vhdl')
-rw-r--r-- | testsuite/synth/arr01/tb_arr04.vhdl | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/testsuite/synth/arr01/tb_arr04.vhdl b/testsuite/synth/arr01/tb_arr04.vhdl new file mode 100644 index 000000000..51801b258 --- /dev/null +++ b/testsuite/synth/arr01/tb_arr04.vhdl @@ -0,0 +1,43 @@ +entity tb_arr04 is +end tb_arr04; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_arr04 is + signal clk : std_logic; + signal rst : std_logic; + signal sel_i : std_logic; + signal sel_o : std_logic; + signal v : std_logic; + signal r : std_logic; +begin + dut: entity work.arr04 + port map (clk => clk, rst => rst, sel_i => sel_i, sel_o => sel_o, + v => v, res => r); + + process + constant siv : std_logic_vector := b"0010"; + constant sov : std_logic_vector := b"0101"; + constant v_v : std_logic_vector := b"0011"; + constant r_v : std_logic_vector := b"0001"; + begin + clk <= '0'; + rst <= '1'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + rst <= '0'; + for i in siv'range loop + sel_i <= siv (i); + sel_o <= sov (i); + v <= v_v (i); + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + assert r = r_v(i) severity failure; + end loop; + wait; + end process; +end behav; |