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author | Tristan Gingold <tgingold@free.fr> | 2019-07-01 18:22:06 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-01 18:22:06 +0200 |
commit | fe35233c6f06c13a6a18db69da774a29a1993966 (patch) | |
tree | 37fe5abfcb6141f3268abcff1c0197c45985abdc /testsuite/synth/arr01/tb_arr01.vhdl | |
parent | 10e0d932d67e90263dfd393be8b3719e26fe6514 (diff) | |
download | ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.tar.gz ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.tar.bz2 ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.zip |
testsuite/synth: add arr01
Diffstat (limited to 'testsuite/synth/arr01/tb_arr01.vhdl')
-rw-r--r-- | testsuite/synth/arr01/tb_arr01.vhdl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/arr01/tb_arr01.vhdl b/testsuite/synth/arr01/tb_arr01.vhdl new file mode 100644 index 000000000..bf3d7c6fa --- /dev/null +++ b/testsuite/synth/arr01/tb_arr01.vhdl @@ -0,0 +1,23 @@ +entity tb_arr01 is +end tb_arr01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_arr01 is + signal v : std_logic_vector(7 downto 0); + signal h : std_logic_vector(3 downto 0); + signal l : std_logic_vector(3 downto 0); +begin + dut: entity work.arr01 + port map (v => v, h => h, l => l); + + process + begin + v <= x"e5"; + wait for 1 ns; + assert h = x"e" severity failure; + assert l = x"5" severity failure; + wait; + end process; +end behav; |