diff options
author | Tristan Gingold <tgingold@free.fr> | 2019-07-01 18:22:06 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2019-07-01 18:22:06 +0200 |
commit | fe35233c6f06c13a6a18db69da774a29a1993966 (patch) | |
tree | 37fe5abfcb6141f3268abcff1c0197c45985abdc /testsuite/synth/arr01/arr04.vhdl | |
parent | 10e0d932d67e90263dfd393be8b3719e26fe6514 (diff) | |
download | ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.tar.gz ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.tar.bz2 ghdl-fe35233c6f06c13a6a18db69da774a29a1993966.zip |
testsuite/synth: add arr01
Diffstat (limited to 'testsuite/synth/arr01/arr04.vhdl')
-rw-r--r-- | testsuite/synth/arr01/arr04.vhdl | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/testsuite/synth/arr01/arr04.vhdl b/testsuite/synth/arr01/arr04.vhdl new file mode 100644 index 000000000..813f366c9 --- /dev/null +++ b/testsuite/synth/arr01/arr04.vhdl @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity arr04 is + port (clk : in std_logic; + rst : std_logic; + sel_i : std_logic; + sel_o : std_logic; + v : std_logic; + res : out std_logic); +end arr04; + +architecture behav of arr04 is + signal reg : std_logic_vector (0 to 1); +begin + -- Reader + process(clk) + begin + if rising_edge (clk) then + if sel_o = '0' then + res <= reg (0); + else + res <= reg (1); + end if; + end if; + end process; + + -- Writer + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + reg <= "00"; + else + if sel_i = '0' then + reg (0) <= v; + else + reg (1) <= v; + end if; + end if; + end if; + end process; +end behav; |