Updated to pyVHDLModel v0.18.0.

4 files changed, 34 insertions, 9 deletions

diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py
index 113e541ac..4b2e47507 100644
--- a/testsuite/pyunit/dom/Expressions.py
+++ b/testsuite/pyunit/dom/Expressions.py
@@ -34,6 +34,7 @@ import ctypes
 from inspect import currentframe
 from pathlib import Path
 from textwrap import dedent
+from typing import TypeVar, Dict
 from unittest import TestCase
 
 
@@ -51,6 +52,13 @@ if __name__ == "__main__":
     exit(1)
 
 
+_DictKey = TypeVar("_DictKey")
+_DictValue = TypeVar("_DictValue")
+
+def firstValue(d: Dict[_DictKey, _DictValue]) -> _DictValue:
+    return next(iter(d.values()))
+
+
 class Expressions(TestCase):
     _root = Path(__file__).resolve().parent.parent
     _design = Design()
@@ -69,7 +77,7 @@ class Expressions(TestCase):
         self._design.Documents.append(document)
 
         # Traverse already to default value expression
-        package: Package = document.Packages[0]
+        package: Package = firstValue(document.Packages)
         item: Constant = package.DeclaredItems[0]
         default: Expression = item.DefaultExpression
 
diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py
index debd401e3..9f53a6cc6 100644
--- a/testsuite/pyunit/dom/Literals.py
+++ b/testsuite/pyunit/dom/Literals.py
@@ -32,6 +32,7 @@
 # ============================================================================
 from pathlib import Path
 from textwrap import dedent
+from typing import TypeVar, Dict
 from unittest import TestCase
 
 from pyVHDLModel.SyntaxModel import ExpressionUnion
@@ -49,6 +50,13 @@ if __name__ == "__main__":
     exit(1)
 
 
+_DictKey = TypeVar("_DictKey")
+_DictValue = TypeVar("_DictValue")
+
+def firstValue(d: Dict[_DictKey, _DictValue]) -> _DictValue:
+    return next(iter(d.values()))
+
+
 class Literals(TestCase):
     _root = Path(__file__).resolve().parent.parent
     _design = Design()
@@ -67,7 +75,7 @@ class Literals(TestCase):
         self._design.Documents.append(document)
 
         # Traverse already to default value expression
-        package: Package = document.Packages[0]
+        package: Package = firstValue(document.Packages)
         item: Constant = package.DeclaredItems[0]
         default: ExpressionUnion = item.DefaultExpression
 
diff --git a/testsuite/pyunit/dom/Sanity.py b/testsuite/pyunit/dom/Sanity.py
index ff5151fb3..54cb4103b 100644
--- a/testsuite/pyunit/dom/Sanity.py
+++ b/testsuite/pyunit/dom/Sanity.py
@@ -50,10 +50,11 @@ _SANITY_TESTS_ROOT = _TESTSUITE_ROOT / "sanity"
 design = Design()
 
 
-@mark.parametrize("file", [str(f.relative_to(_TESTSUITE_ROOT)) for f in _SANITY_TESTS_ROOT.glob("**/*.vhdl")])
-def test_AllVHDLSources(file):
+@mark.parametrize("parameters", [f"{i}:{f.relative_to(_TESTSUITE_ROOT)}" for i, f in enumerate(_SANITY_TESTS_ROOT.glob("**/*.vhdl"))])
+def test_AllVHDLSources(parameters):
+    id, file = parameters.split(":")
     filePath = _TESTSUITE_ROOT / file
 
-    lib = design.GetLibrary("sanity")
+    lib = design.GetLibrary(f"sanity_{id}")
     document = Document(filePath)
     design.AddDocument(document, lib)
diff --git a/testsuite/pyunit/dom/Simple.py b/testsuite/pyunit/dom/Simple.py
index 32033609d..82dd8579e 100644
--- a/testsuite/pyunit/dom/Simple.py
+++ b/testsuite/pyunit/dom/Simple.py
@@ -31,6 +31,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
 from pathlib import Path
+from typing import TypeVar, Dict
 from unittest import TestCase
 
 from pyGHDL.dom.NonStandard import Design, Document
@@ -42,6 +43,13 @@ if __name__ == "__main__":
     exit(1)
 
 
+_DictKey = TypeVar("_DictKey")
+_DictValue = TypeVar("_DictValue")
+
+def firstValue(d: Dict[_DictKey, _DictValue]) -> _DictValue:
+    return next(iter(d.values()))
+
+
 class SimpleEntity(TestCase):
     _root = Path(__file__).resolve().parent.parent
     _filename: Path = _root / "dom/examples/SimpleEntity.vhdl"
@@ -71,7 +79,7 @@ class SimpleEntity(TestCase):
 
         self.assertEqual(1, len(design.Documents[0].Entities))
 
-        entity = design.Documents[0].Entities[0]
+        entity = firstValue(design.Documents[0].Entities)
         self.assertEqual("Counter", entity.Identifier)
         print()
         print(entity.Documentation)
@@ -84,7 +92,7 @@ class SimpleEntity(TestCase):
 
         self.assertEqual(1, len(design.Documents[0].Architectures))
 
-        architecture = design.Documents[0].Architectures[0]
+        architecture = firstValue(firstValue(design.Documents[0].Architectures))
         self.assertEqual("rtl", architecture.Identifier)
         print()
         print(architecture.Documentation)
@@ -120,7 +128,7 @@ class SimplePackage(TestCase):
 
         self.assertEqual(1, len(design.Documents[0].Packages))
 
-        package = design.Documents[0].Packages[0]
+        package = firstValue(design.Documents[0].Packages)
         self.assertEqual("utilities", package.Identifier)
         print()
         print(package.Documentation)
@@ -133,7 +141,7 @@ class SimplePackage(TestCase):
 
         self.assertEqual(1, len(design.Documents[0].PackageBodies))
 
-        packageBodies = design.Documents[0].PackageBodies[0]
+        packageBodies = firstValue(design.Documents[0].PackageBodies)
         self.assertEqual("utilities", packageBodies.Identifier)
         print()
         print(packageBodies.Documentation)