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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-07-28 09:00:03 +0200 |
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committer | umarcor <unai.martinezcorral@ehu.eus> | 2021-08-23 16:35:32 +0200 |
commit | 20b636decb9c502891fbf5f9a15cf8e7126904a5 (patch) | |
tree | c429b7f0026cc032c18fbb8b92b26484e75120f7 /testsuite/pyunit | |
parent | ee933a5fc78353e7a87fe64616b25387fdc12b2b (diff) | |
download | ghdl-20b636decb9c502891fbf5f9a15cf8e7126904a5.tar.gz ghdl-20b636decb9c502891fbf5f9a15cf8e7126904a5.tar.bz2 ghdl-20b636decb9c502891fbf5f9a15cf8e7126904a5.zip |
Handle instantiations 1/2.
Diffstat (limited to 'testsuite/pyunit')
-rw-r--r-- | testsuite/pyunit/Current.vhdl | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index eae346375..3c518cce4 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -85,7 +85,7 @@ architecture behav of entity_1 is package inner_pack is end package; begin - process(Clock) + proc: process(Clock) begin if rising_edge(Clock) then if Reset = '1' then @@ -95,6 +95,36 @@ begin end if; end if; end process; + + a <= b; + + + inst1: entity work.counter1(rtl) + generic map ( + BITS => 8 + ) + port map ( + clk => Clock + ); + + inst2: component counter2 + port map ( + clk => Clock + ); + + inst3: configuration counter3 + port map ( + clk => Clock + ); + + blk: block + begin + inst4: entity work.counter4(rtl) + port map ( + clk => Clock + ); + end block; + end architecture behav; package package_1 is |