Add testcase from #731

3 files changed, 55 insertions, 0 deletions

diff --git a/testsuite/gna/issue731/adder.vhdl b/testsuite/gna/issue731/adder.vhdl
new file mode 100644
index 000000000..1a214b91a
--- /dev/null
+++ b/testsuite/gna/issue731/adder.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity Adder is
+	generic (gWidth : natural);
+	port(
+		iA : in std_ulogic_vector(gWidth-1 downto 0);
+		iB : in std_ulogic_vector(gWidth-1 downto 0);
+		
+		oCarry: out std_ulogic;
+		oRes : out std_ulogic_vector(gWidth-1 downto 0)
+	);
+end entity Adder;
+
+architecture RTL of Adder is
+begin
+	(oCarry, oRes) <= std_ulogic_vector(unsigned('0' & iA) + unsigned('0' & iB));
+end architecture RTL;
diff --git a/testsuite/gna/issue731/tbadder.vhdl b/testsuite/gna/issue731/tbadder.vhdl
new file mode 100644
index 000000000..465280756
--- /dev/null
+++ b/testsuite/gna/issue731/tbadder.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.env.all;
+
+entity tbAdder is
+end entity tbAdder;
+
+architecture Bhv of tbAdder is
+	constant cWidth : natural := 8;	
+	signal iA, iB : std_ulogic_vector(cWidth-1 downto 0) := (others => '0');
+	signal oRes : std_ulogic_vector(cWidth-1 downto 0);
+	signal oCarry : std_ulogic;
+begin
+	UUT: entity work.Adder
+		generic map(
+			gWidth => cWidth
+		)
+		port map(
+			iA     => iA,
+			iB     => iB,
+			oCarry => oCarry,
+			oRes   => oRes
+		);	
+end architecture Bhv;
diff --git a/testsuite/gna/issue731/testsuite.sh b/testsuite/gna/issue731/testsuite.sh
new file mode 100755
index 000000000..6af334ddd
--- /dev/null
+++ b/testsuite/gna/issue731/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze adder.vhdl tbadder.vhdl
+elab_simulate tbadder
+
+clean
+
+echo "Test successful"