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author | Tristan Gingold <tgingold@free.fr> | 2018-04-24 18:57:39 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-04-24 18:57:39 +0200 |
commit | 9adcbde96c2f848c6323b1468b04d28de1976c33 (patch) | |
tree | 8663ad20d3e7491e8ef74bc9339d4e933983604c /testsuite/gna | |
parent | 0c5810f8f576f59a92a2863c4e6408b04590e863 (diff) | |
download | ghdl-9adcbde96c2f848c6323b1468b04d28de1976c33.tar.gz ghdl-9adcbde96c2f848c6323b1468b04d28de1976c33.tar.bz2 ghdl-9adcbde96c2f848c6323b1468b04d28de1976c33.zip |
Add reproducer for #559
Diffstat (limited to 'testsuite/gna')
-rw-r--r-- | testsuite/gna/issue559/dut.vhdl | 68 | ||||
-rwxr-xr-x | testsuite/gna/issue559/testsuite.sh | 10 |
2 files changed, 78 insertions, 0 deletions
diff --git a/testsuite/gna/issue559/dut.vhdl b/testsuite/gna/issue559/dut.vhdl new file mode 100644 index 000000000..b602c32e2 --- /dev/null +++ b/testsuite/gna/issue559/dut.vhdl @@ -0,0 +1,68 @@ +-- +-- dut +-- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity dut is +Generic ( + TARGETS_ADDR : std_logic_vector +); +end dut; +architecture a of dut is + + signal slv : std_logic_vector(1 downto 0); + + type slv_arr_t is array (0 to 1) of std_logic_vector(slv'range); + + function addr_arr_init ( + arg : std_logic_vector + ) return slv_arr_t is + variable v : slv_arr_t; + begin + report "arg'length="&positive'image(arg'length); + report "v(0)'length="&positive'image(v(0)'length); + + -- Bound check error + v(0) := arg(1 downto 0); + + -- No bound check error + --v(0) := arg; + return v; + end function; + + constant ADDR_ARR : slv_arr_t := addr_arr_init(TARGETS_ADDR); +begin + +end a; + +-- +-- tb +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb is +end entity; + +architecture bench of tb is + constant C_SLV : std_logic_vector(1 downto 0) := "00"; +begin + + dut : entity work.dut + generic map ( + -- Bound check error + TARGETS_ADDR => "00" + -- No bound check error + --TARGETS_ADDR => C_SLV + ); + + stimulus : process + begin + report "pass"; + wait; + end process; + +end bench; diff --git a/testsuite/gna/issue559/testsuite.sh b/testsuite/gna/issue559/testsuite.sh new file mode 100755 index 000000000..343740566 --- /dev/null +++ b/testsuite/gna/issue559/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze dut.vhdl +elab_simulate_failure tb + +clean + +echo "Test successful" |