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author | Tristan Gingold <tgingold@free.fr> | 2018-11-23 04:30:01 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-11-23 04:30:01 +0100 |
commit | 996b72a7fe8eb06512467c9acbb47b3af4837136 (patch) | |
tree | 81cdb97f3e82592388f3409f0f345a8768840575 /testsuite/gna | |
parent | f2c4cfadb13dd5eef1979069317e5c6ee224c908 (diff) | |
download | ghdl-996b72a7fe8eb06512467c9acbb47b3af4837136.tar.gz ghdl-996b72a7fe8eb06512467c9acbb47b3af4837136.tar.bz2 ghdl-996b72a7fe8eb06512467c9acbb47b3af4837136.zip |
Add testcase for #692
Diffstat (limited to 'testsuite/gna')
-rw-r--r-- | testsuite/gna/issue692/ent.vhdl | 11 | ||||
-rw-r--r-- | testsuite/gna/issue692/repro.vhdl | 21 | ||||
-rw-r--r-- | testsuite/gna/issue692/repro_proc.vhdl | 19 | ||||
-rwxr-xr-x | testsuite/gna/issue692/testsuite.sh | 14 |
4 files changed, 65 insertions, 0 deletions
diff --git a/testsuite/gna/issue692/ent.vhdl b/testsuite/gna/issue692/ent.vhdl new file mode 100644 index 000000000..beca07efe --- /dev/null +++ b/testsuite/gna/issue692/ent.vhdl @@ -0,0 +1,11 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb is end entity; +architecture arch of tb is + signal reproducer: unsigned(15 downto 0); +begin + reproducer <= to_unsigned(integer(0.0), 10**7); +end arch; + diff --git a/testsuite/gna/issue692/repro.vhdl b/testsuite/gna/issue692/repro.vhdl new file mode 100644 index 000000000..d5cc42312 --- /dev/null +++ b/testsuite/gna/issue692/repro.vhdl @@ -0,0 +1,21 @@ +entity repro is +end; + +architecture behav of repro +is + function test (l : natural) return boolean is + variable v : bit_vector (l - 1 downto 0); + begin + assert v (l / 2) = '0'; + assert v (0) = '0'; + assert v (l - 1) = '0'; + return True; + end test; +begin + process + variable res : boolean; + begin + res := test (128 * 1024); + wait; + end process; +end behav; diff --git a/testsuite/gna/issue692/repro_proc.vhdl b/testsuite/gna/issue692/repro_proc.vhdl new file mode 100644 index 000000000..29b11cad9 --- /dev/null +++ b/testsuite/gna/issue692/repro_proc.vhdl @@ -0,0 +1,19 @@ +entity repro is +end; + +architecture behav of repro +is + procedure test (l : natural) is + variable v : bit_vector (l - 1 downto 0); + begin + assert v (l / 2) = '0'; + assert v (0) = '0'; + assert v (l - 1) = '0'; + end test; +begin + process + begin + test (128 * 1024); + wait; + end process; +end behav; diff --git a/testsuite/gna/issue692/testsuite.sh b/testsuite/gna/issue692/testsuite.sh new file mode 100755 index 000000000..cbd59e81c --- /dev/null +++ b/testsuite/gna/issue692/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze ent.vhdl +elab_simulate_failure tb + +analyze repro.vhdl +elab_simulate_failure repro --max-stack-alloc=64 +elab_simulate repro --max-stack-alloc=256 + +clean + +echo "Test successful" |