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authorTristan Gingold <tgingold@free.fr>2017-01-16 06:12:08 +0100
committerTristan Gingold <tgingold@free.fr>2017-01-16 06:12:08 +0100
commit860919f436a46383035c574fe872dcb3fc05de9e (patch)
treec43189f9daa175df85330d891b33ffac4267dd0e /testsuite/gna
parentb42069e0f4538bbaffbc015359770018caa9b209 (diff)
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issue256: Run testcase and testcase2.
Diffstat (limited to 'testsuite/gna')
-rw-r--r--testsuite/gna/issue256/testcase2.vhd4
-rw-r--r--testsuite/gna/issue256/testcase2_testbench.vhd26
-rwxr-xr-xtestsuite/gna/issue256/testsuite.sh8
3 files changed, 36 insertions, 2 deletions
diff --git a/testsuite/gna/issue256/testcase2.vhd b/testsuite/gna/issue256/testcase2.vhd
index 2f8b9a4ca..4b9928c8d 100644
--- a/testsuite/gna/issue256/testcase2.vhd
+++ b/testsuite/gna/issue256/testcase2.vhd
@@ -3,3 +3,7 @@ entity testcase2 is
begin
check: assert clk'delayed'last_event >= 10 ns;
end entity testcase2;
+
+architecture empty of testcase2 is
+begin
+end empty;
diff --git a/testsuite/gna/issue256/testcase2_testbench.vhd b/testsuite/gna/issue256/testcase2_testbench.vhd
new file mode 100644
index 000000000..6a27db515
--- /dev/null
+++ b/testsuite/gna/issue256/testcase2_testbench.vhd
@@ -0,0 +1,26 @@
+entity testcase2_testbench is
+end entity testcase2_testbench;
+
+architecture bench of testcase2_testbench is
+ signal clk: bit;
+begin
+ dut: entity work.testcase2(empty) port map(clk => clk);
+
+ stimulus: process is
+ begin
+ -- Valid low and high pulses
+ clk <= '0';
+ wait for 10 ns;
+ clk <= '1';
+ wait for 10 ns;
+ -- Confirm that we're timing events, not transactions
+ clk <= '1';
+ wait for 5 ns;
+ -- Now send a short pulse to make the assertion fire
+ clk <= '0';
+ wait for 5 ns;
+ -- Assertion should fire here, at 30ns
+ clk <= '1';
+ wait;
+ end process stimulus;
+end architecture bench;
diff --git a/testsuite/gna/issue256/testsuite.sh b/testsuite/gna/issue256/testsuite.sh
index f9ec0e8cc..56673760a 100755
--- a/testsuite/gna/issue256/testsuite.sh
+++ b/testsuite/gna/issue256/testsuite.sh
@@ -3,11 +3,15 @@
. ../../testenv.sh
analyze testcase.vhd
-analyze testcase2.vhd
-analyze testcase3.vhd
analyze testcase_testbench.vhd
elab_simulate testcase_testbench
+analyze testcase2.vhd
+analyze testcase2_testbench.vhd
+elab_simulate testcase2_testbench
+
+analyze testcase3.vhd
+
clean
echo "Test successful"