testsuite/gna: add a test for #1843

3 files changed, 57 insertions, 0 deletions

diff --git a/testsuite/gna/issue1843/counter.vhdl b/testsuite/gna/issue1843/counter.vhdl
new file mode 100644
index 000000000..1effc4b68
--- /dev/null
+++ b/testsuite/gna/issue1843/counter.vhdl
@@ -0,0 +1,28 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY counter IS
+  GENERIC(
+    WIDTH : positive := 32
+  );
+  PORT( 
+    clk        : IN     std_logic
+  );
+END ENTITY counter;
+
+ARCHITECTURE rtl OF counter IS
+  CONSTANT UPPER_LIMIT : unsigned((WIDTH-1) DOWNTO 0) := (OTHERS => '1');
+  SIGNAL count : unsigned((WIDTH-1) DOWNTO 0);
+BEGIN
+
+  p_counter : PROCESS (clk)
+  BEGIN
+    IF (rising_edge(clk)) THEN
+      IF ((('0', count) + 1) < UPPER_LIMIT) THEN
+        count <= count + 1;
+      END IF;
+    END IF;
+  END PROCESS;
+
+END ARCHITECTURE rtl;
diff --git a/testsuite/gna/issue1843/repro.vhdl b/testsuite/gna/issue1843/repro.vhdl
new file mode 100644
index 000000000..b7a7b589e
--- /dev/null
+++ b/testsuite/gna/issue1843/repro.vhdl
@@ -0,0 +1,18 @@
+ENTITY repro IS
+  GENERIC(WIDTH : positive := 32);
+  PORT(clk        : IN     bit);
+END;
+
+ARCHITECTURE rtl OF repro IS
+  CONSTANT UPPER_LIMIT : bit_vector(WIDTH DOWNTO 0) := (OTHERS => '1');
+  SIGNAL count : bit_vector((WIDTH-1) DOWNTO 0);
+BEGIN
+
+  p_counter : PROCESS (clk)
+  BEGIN
+    IF ('0', count) /= UPPER_LIMIT then
+      count(0) <= '1';
+    END IF;
+  END PROCESS;
+
+END ARCHITECTURE rtl;
diff --git a/testsuite/gna/issue1843/testsuite.sh b/testsuite/gna/issue1843/testsuite.sh
new file mode 100755
index 000000000..067817bb4
--- /dev/null
+++ b/testsuite/gna/issue1843/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze counter.vhdl
+elab_simulate counter
+
+clean
+
+echo "Test successful"