Add reproducer for issue30

5 files changed, 12931 insertions, 0 deletions

diff --git a/testsuite/gna/issue30/alu.vhdl b/testsuite/gna/issue30/alu.vhdl
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index 000000000..10ae2e6ef
--- /dev/null
+++ b/testsuite/gna/issue30/alu.vhdl
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+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library work;
+use		work.definitions.all;
+
+entity ccf_operation is
+port(
+	flags_in:	in	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_ccf_operation of ccf_operation is
+begin
+	-- A point of disagreement has been found between the Z80 user manual
+	-- and Lance Levinthal's book entitled "Z80 Assembly Language Programming".
+	-- The Z80 user manual says the half-carry bit gets the previous carry;
+	-- Levinthal says the half-carry bit is unchanged.  For now, go with
+	-- Levinthal's version as the Z80 users manual is inconsistent with
+	-- itself on other instructions.  At this time, no such inconsistencies
+	-- have been found with Levinthal's work.
+
+	flags_out <= (	carry_bit => not flags_in(carry_bit),
+					half_carry_bit => flags_in(carry_bit),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library work;
+use		work.definitions.all;
+
+entity sll8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_sll8bit of sll8bit is
+
+signal	sll_result:	std_logic_vector(7 downto 0);
+begin
+	-- This operation is not documented by Zilog, but seems to work in their
+	-- finished chip.  This code may not work the same way as the Z80 hardware
+	-- works.  The functionality is assumed from the SRL instruction.
+
+	sll_result <= operand(6 downto 0) & '0';
+
+	output <= sll_result;
+	flags_out <= (	carry_bit => operand(7),
+					zero_bit => not (sll_result(7) or sll_result(6) or sll_result(5) or sll_result(4) or
+									 sll_result(3) or sll_result(2) or sll_result(1) or sll_result(0)),
+					parity_overflow_bit => not (sll_result(7) xor sll_result(6) xor sll_result(5) xor
+												sll_result(4) xor sll_result(3) xor sll_result(2) xor
+												sll_result(1) xor sll_result(0)),
+					sign_bit => operand(6),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library work;
+use		work.definitions.all;
+
+entity srl8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_srl8bit of srl8bit is
+
+signal	srl_result:	std_logic_vector(7 downto 0);
+
+begin
+	srl_result <= '0' & operand(7 downto 1);
+
+	output <= srl_result;
+	flags_out <= (	carry_bit => operand(0),
+					zero_bit => not (srl_result(7) or srl_result(6) or srl_result(5) or srl_result(4) or
+									 srl_result(3) or srl_result(2) or srl_result(1) or srl_result(0)),
+					parity_overflow_bit => not (srl_result(7) xor srl_result(6) xor srl_result(5) xor
+												srl_result(4) xor srl_result(3) xor srl_result(2) xor
+												srl_result(1) xor srl_result(0)),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library work;
+use		work.definitions.all;
+
+entity and8bit is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_and8bit of and8bit is
+
+signal	and_result:		std_logic_vector(7 downto 0);
+
+begin
+	and_result <= operand1 and operand2;
+
+	flags_out <= (	sign_bit => and_result(7),
+					zero_bit => not (and_result(7) or and_result(6) or and_result(5) or and_result(4) or
+									 and_result(3) or and_result(2) or and_result(1) or and_result(0)),
+					half_carry_bit => '1',
+					parity_overflow_bit => not (and_result(7) xor and_result(6) xor and_result(5) xor
+												and_result(4) xor and_result(3) xor and_result(2) xor
+												and_result(1) xor and_result(0)),
+					others => '0');
+
+	output <= and_result;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity or8bit is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_or8bit of or8bit is
+
+signal	or_result:		std_logic_vector(7 downto 0);
+
+begin
+	or_result <= operand1 or operand2;
+
+	output <= or_result;
+	flags_out <= (	sign_bit => or_result(7),
+					half_carry_bit => '1',
+					zero_bit => not (or_result(7) or or_result(6) or or_result(5) or or_result(4) or
+									 or_result(3) or or_result(2) or or_result(1) or or_result(0)),
+					parity_overflow_bit => not (or_result(7) xor or_result(6) xor or_result(5) xor
+												or_result(4) xor or_result(3) xor or_result(2) xor
+												or_result(1) xor or_result(0)),
+					others => '0');
+end;
+
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity sra8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_sra8bit of sra8bit is
+
+signal	sra_result:	std_logic_vector(7 downto 0);
+
+begin
+	sra_result <= operand(7) & operand(7 downto 1);
+
+	output <= sra_result;
+	flags_out <= (	carry_bit => operand(0),
+					zero_bit => not (sra_result(7) or sra_result(6) or sra_result(5) or sra_result(4) or
+									 sra_result(3) or sra_result(2) or sra_result(1) or sra_result(0)),
+					parity_overflow_bit => not (sra_result(7) xor sra_result(6) xor sra_result(5) xor
+												sra_result(4) xor sra_result(3) xor sra_result(2) xor
+												sra_result(1) xor sra_result(0)),
+					sign_bit => operand(7),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity xor8bit is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_xor8bit of xor8bit is
+
+signal	xor_result:		std_logic_vector(7 downto 0);
+
+begin
+	xor_result <= operand1 xor operand2;
+
+	output <= xor_result;
+	flags_out <= (	sign_bit => xor_result(7),
+					half_carry_bit => '1',
+					zero_bit => not (xor_result(7) or xor_result(6) or xor_result(5) or xor_result(4) or
+									 xor_result(3) or xor_result(2) or xor_result(1) or xor_result(0)),
+					parity_overflow_bit => not (xor_result(7) xor xor_result(6) xor xor_result(5) xor
+												xor_result(4) xor xor_result(3) xor xor_result(2) xor
+												xor_result(1) xor xor_result(0)),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity sla8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_sla8bit of sla8bit is
+
+signal	sla_result:	std_logic_vector(7 downto 0);
+
+begin
+	sla_result <= operand(6 downto 0) & '0';
+
+	output <= sla_result;
+	flags_out <= (	sign_bit => sla_result(7),
+					half_carry_bit => '1',
+					zero_bit => not (sla_result(7) or sla_result(6) or sla_result(5) or sla_result(4) or
+									 sla_result(3) or sla_result(2) or sla_result(1) or sla_result(0)),
+					parity_overflow_bit => not (sla_result(7) xor sla_result(6) xor sla_result(5) xor
+												sla_result(4) xor sla_result(3) xor sla_result(2) xor
+												sla_result(1) xor sla_result(0)),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity subtractor is
+port(
+	minuend, subtrahend:	in	std_logic;
+	borrow_in:				in	std_logic;
+	difference:				out	std_logic;
+	borrow_out:				out	std_logic
+);
+end;
+
+architecture struct_subtractor of subtractor is
+begin
+
+-- These expressions were derived from the truth table of a single bit subtractor and simplified with
+-- a Karnaugh map.
+
+	difference <=	(borrow_in and (not minuend) and (not subtrahend)) or
+					((not borrow_in) and (not minuend) and subtrahend) or
+					(borrow_in and minuend and subtrahend) or
+					((not borrow_in) and minuend and (not subtrahend));
+
+	borrow_out <=	(not minuend and subtrahend) or
+					(borrow_in and (not minuend)) or
+					(borrow_in and subtrahend);
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity subtractorN is
+generic(
+	N:	positive
+);
+port(
+	minuend:	in	std_logic_vector((N-1) downto 0);
+	subtrahend:	in	std_logic_vector((N-1) downto 0);
+	borrow_in:	in	std_logic;
+	difference:	out	std_logic_vector((N-1) downto 0);
+	borrow_out:	out	std_logic
+);
+end;
+
+architecture struct_subtractorN of subtractorN is
+component subtractor is
+port(
+	minuend, subtrahend:	in	std_logic;
+	borrow_in:				in	std_logic;
+	difference:				out	std_logic;
+	borrow_out:				out	std_logic
+);
+end component;
+
+signal	borrow:	std_logic_vector(N downto 0);
+
+begin
+--	These expressions were derived from the truth table of a single bit subtractor and simplified with a
+--	Karnaugh map.
+--	d = difference, m = minuend, s = subtrahend, b = borrow
+--
+--	d(i) =	(b(i) and (not m(i)) and (not s(i))) or
+--			((not b(i)) and (not m(i)) and s(i)) or
+--			(b(i) and m(i) and s(i)) or
+--			((not b(i)) and m(i) and (not s(i)))
+--
+--	b(i+1) =	(not m(i) and s(i)) or
+--				(b(i) and (not m(i))) or
+--				(b(i) and s(i)
+
+	borrow(0) <= borrow_in;
+
+	u1: for i in 0 to (N-1) generate
+		u: subtractor port map(
+				minuend => minuend(i),
+				subtrahend => subtrahend(i),
+				borrow_in => borrow(i),
+				difference => difference(i),
+				borrow_out => borrow(i+1)
+			);
+		end generate;
+
+	borrow_out <= borrow(N);
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity subtractor8x2 is
+port(
+	minuend, subtrahend:	in	std_logic_vector(7 downto 0);
+	borrow_in:				in	std_logic;
+	difference:				out	std_logic_vector(7 downto 0);
+	flags_out:				out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_subtractor8x2 of subtractor8x2 is
+component subtractor is
+port(
+	minuend, subtrahend:	in	std_logic;
+	borrow_in:				in	std_logic;
+	difference:				out	std_logic;
+	borrow_out:				out	std_logic
+);
+end component;
+
+signal	borrow:	std_logic_vector(8 downto 0);
+signal	d:		std_logic_vector(7 downto 0);
+
+begin
+	borrow(0) <= borrow_in;
+
+	u1: for i in 0 to 7 generate
+		u: subtractor port map(
+				minuend => minuend(i),
+				subtrahend => subtrahend(i),
+				borrow_in => borrow(i),
+				difference => d(i),
+				borrow_out => borrow(i+1)
+			);
+		end generate;
+
+	difference <= d;
+
+	flags_out <= (	sign_bit => d(7),
+					zero_bit => not (d(0) or d(1) or d(2) or d(3) or d(4) or d(5) or d(6) or d(7)),
+					half_carry_bit => borrow(4),
+					parity_overflow_bit => (minuend(7) xor subtrahend(7)) and (minuend(7) xor d(7)),
+					add_sub_bit => '1',
+					carry_bit => borrow(8),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity adder is
+port(
+	addend, augend:	in	std_logic;
+	carry_in:		in	std_logic;
+	sum:			out	std_logic;
+	carry_out:		out	std_logic
+);
+end;
+
+architecture struct_adder of adder is
+begin
+--	These expressions are derived from a single bit full adder truth table and simplified with a
+--	Karnaugh map.
+	sum <=	((not (carry_in)) and (not addend) and augend) or
+			((not carry_in) and addend and (not augend)) or
+			(carry_in and (not addend) and (not augend)) or
+			(carry_in and addend and augend);
+
+	carry_out <=	(addend and augend) or
+					(carry_in and addend) or
+					(carry_in and augend);
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity adderN is
+generic(
+	N:	positive
+);
+port(
+	addend:		in	std_logic_vector((N-1) downto 0);
+	augend:		in	std_logic_vector((N-1) downto 0);
+	carry_in:	in	std_logic;
+	sum:		out	std_logic_vector((N-1) downto 0);
+	carry_out:	out	std_logic
+);
+end;
+
+-- Tested with Modelsim 2015/12/11, works.
+
+architecture struct_adderN of adderN is
+component adder is
+port(
+	addend, augend:	in	std_logic;
+	carry_in:		in	std_logic;
+	sum:			out	std_logic;
+	carry_out:		out	std_logic
+);
+end component;
+
+signal	carry:	std_logic_vector(N downto 0);
+
+begin
+	carry(0) <= carry_in;
+
+	u1: for i in 0 to (N-1) generate
+		u: adder port map(
+				addend => addend(i),
+				augend => augend(i),
+				carry_in => carry(i),
+				sum => sum(i),
+				carry_out => carry(i+1)
+			);
+		end generate;
+
+	carry_out <= carry(N);
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity adder8x2 is
+port(
+	addend, augend:		in	std_logic_vector(7 downto 0);
+	carry_in:			in	std_logic;
+	sum:				out	std_logic_vector(7 downto 0);
+	flags_out:			out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+-- The adderN version is not used because access to carry out of bit 3 is required.
+
+architecture struct_adder8x2 of adder8x2 is
+component adder is
+port(
+	addend, augend:	in	std_logic;
+	carry_in:		in	std_logic;
+	sum:			out	std_logic;
+	carry_out:		out	std_logic
+);
+end component;
+
+signal	result:	std_logic_vector(7 downto 0);
+signal	carry:	std_logic_vector(8 downto 0);
+
+begin
+	carry(0) <= carry_in;
+
+	u1: for i in 0 to 7 generate
+		u: adder port map(
+				addend => addend(i),
+				augend => augend(i),
+				carry_in => carry(i),
+				sum => result(i),
+				carry_out => carry(i+1)
+			);
+		end generate;
+
+	sum <= result;
+	flags_out <= (	sign_bit => result(7),
+					zero_bit => not (result(7) or result(6) or result(5) or result(4) or
+									 result(3) or result(2) or result(1) or result(0)),
+					half_carry_bit => carry(4),
+					parity_overflow_bit => not	(addend(7) xor augend(7)) and
+												(addend(7) xor result(7)),
+					add_sub_bit => '0',
+					carry_bit => carry(8),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity cpl is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_cpl of cpl is
+begin
+	output <= not operand;
+	flags_out <= (	half_carry_bit => '1',
+					add_sub_bit => '1',
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity rlc8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_rlc8bit of rlc8bit is
+
+signal	rlc_result:	std_logic_vector(7 downto 0);
+
+begin
+	rlc_result(7 downto 1) <= operand(6 downto 0);
+	rlc_result(0) <= operand(7);
+
+	output <= rlc_result;
+	flags_out <= (	carry_bit => operand(7),
+					parity_overflow_bit => not (rlc_result(7) xor rlc_result(6) xor rlc_result(5) xor
+												rlc_result(4) xor rlc_result(3) xor rlc_result(2) xor
+												rlc_result(1) xor rlc_result(0)),
+					zero_bit => not (rlc_result(7) or rlc_result(6) or rlc_result(5) or rlc_result(4) or
+									 rlc_result(3) or rlc_result(2) or rlc_result(1) or rlc_result(0)),
+					sign_bit => rlc_result(7),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity rrc8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_rrc8bit of rrc8bit is
+
+signal	rrc_result:	std_logic_vector(7 downto 0);
+
+begin
+	rrc_result(6 downto 0) <= operand(7 downto 1);
+	rrc_result(7) <= operand(0);
+
+	output <= rrc_result;
+	flags_out <= (	carry_bit => operand(0),
+					zero_bit => not (rrc_result(7) or rrc_result(6) or rrc_result(5) or rrc_result(4) or
+									 rrc_result(3) or rrc_result(2) or rrc_result(1) or rrc_result(0)),
+					parity_overflow_bit => not (rrc_result(7) xor rrc_result(6) xor rrc_result(5) xor
+												rrc_result(4) xor rrc_result(3) xor rrc_result(2) xor
+												rrc_result(1) xor rrc_result(0)),
+					sign_bit => operand(0),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity rl8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	carry_in:	in	std_logic;
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_rl8bit of rl8bit is
+
+signal	rl_result:	std_logic_vector(7 downto 0);
+
+begin
+	rl_result (7 downto 1) <= operand(6 downto 0);
+	rl_result(0) <= carry_in;
+
+	output <= rl_result;
+	flags_out <= (	carry_bit => operand(7),
+					zero_bit => not (rl_result(7) or rl_result(6) or rl_result(5) or rl_result(4) or
+									 rl_result(3) or rl_result(2) or rl_result(1) or rl_result(0)),
+					parity_overflow_bit => not ((rl_result(7) xor rl_result(6) xor rl_result(5) xor
+												 rl_result(4) xor rl_result(3) xor rl_result(2) xor
+												 rl_result(1) xor rl_result(0))),
+					sign_bit => operand(6),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity rr8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	carry_in:	in	std_logic;
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_rr8bit of rr8bit is
+
+signal	rr_result:	std_logic_vector(7 downto 0);
+
+begin
+	rr_result(6 downto 0) <= operand(7 downto 1);
+	rr_result(7) <= carry_in;
+
+	output <= rr_result;
+	flags_out <= (	carry_bit => operand(0),
+					zero_bit => not (rr_result(7) or rr_result(6) or rr_result(5) or rr_result(4) or
+									 rr_result(3) or rr_result(2) or rr_result(1) or rr_result(0)),
+					parity_overflow_bit => not (rr_result(7) xor rr_result(6) xor rr_result(5) xor
+												rr_result(4) xor rr_result(3) xor rr_result(2) xor
+												rr_result(1) xor rr_result(0)),
+					sign_bit => carry_in,
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity daa is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	flags_in:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Untested, this is nothing more than a stub with code to prevent unassigned variable warnings/errors.
+
+architecture struct_daa of daa is
+begin
+	output <= operand;
+	flags_out <= flags_in;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity bit_op is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_bit_op of bit_op is
+
+signal	zero:	std_logic;
+
+begin
+	zero <= '1' when (operand1 and operand2) = x"00" else '0';
+
+	flags_out <= (	zero_bit => zero,
+					half_carry_bit => '1',
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity rld is
+port(
+	primary_op:			in	std_logic_vector(7 downto 0);
+	secondary_op:		in	std_logic_vector(7 downto 0);
+	result:				out	std_logic_vector(7 downto 0);
+	secondary_result:	out	std_logic_vector(7 downto 0);
+	flags_out:			out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_rld of rld is
+
+signal	primary_result:	std_logic_vector(7 downto 0);
+
+begin
+	primary_result(7 downto 4) <= primary_op(7 downto 4);
+	primary_result(3 downto 0) <= secondary_op(7 downto 4);
+	result <= primary_result;
+	secondary_result(7 downto 4) <= secondary_op(3 downto 0);
+	secondary_result(3 downto 0) <= primary_op(3 downto 0);
+	flags_out <= (	sign_bit => primary_result(7),
+					zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
+									 primary_result(4) or primary_result(3) or primary_result(2) or
+									 primary_result(1) or primary_result(0)),
+					parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
+												primary_result(5) xor primary_result(4) xor
+												primary_result(3) xor primary_result(2) xor
+												primary_result(1) xor primary_result(0)),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity rrd is
+port(
+	primary_op:			in	std_logic_vector(7 downto 0);
+	secondary_op:		in	std_logic_vector(7 downto 0);
+	result:				out	std_logic_vector(7 downto 0);
+	secondary_result:	out	std_logic_vector(7 downto 0);
+	flags_out:			out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_rrd of rrd is
+
+signal	primary_result:	std_logic_vector(7 downto 0);
+
+begin
+	primary_result(7 downto 4) <= primary_op(7 downto 4);
+	primary_result(3 downto 0) <= secondary_op(3 downto 0);
+	result <= primary_result;
+	secondary_result(7 downto 4) <= primary_op(3 downto 0);
+	secondary_result(3 downto 0) <= secondary_op(7 downto 4);
+	flags_out <= (	sign_bit => primary_result(7),
+					zero_bit => not (primary_result(7) or primary_result(6) or primary_result(5) or
+									 primary_result(4) or primary_result(3) or primary_result(2) or
+									 primary_result(1) or primary_result(0)),
+					parity_overflow_bit => not (primary_result(7) xor primary_result(6) xor
+												primary_result(5) xor primary_result(4) xor
+												primary_result(3) xor primary_result(2) xor
+												primary_result(1) xor primary_result(0)),
+					others => '0');
+
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity in_rc_flags is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_in_rc_flags of in_rc_flags is
+begin
+	flags_out <= (	zero_bit => not (operand(7) or operand(6) or operand(5) or operand(4) or
+									 operand(3) or operand(2) or operand(1) or operand(0)),
+					sign_bit => operand(7),
+					parity_overflow_bit => not (operand(7) xor operand(6) xor operand(5) xor
+												operand(4) xor operand(3) xor operand(2) xor
+												operand(1) xor operand(0)),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity bmtc is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested with Modelsim 2015/11/25, works.
+
+architecture struct_bmtc of bmtc is
+
+signal	result:	std_logic_vector(7 downto 0);
+
+begin
+	result <= operand1 or operand2;
+	output <= result;
+	flags_out <= (	parity_overflow_bit => not (result(7) or result(6) or result(5) or result(4) or
+												result(3) or result(2) or result(1) or result(0)),
+					others => '0');
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.definitions.all;
+
+entity alu is
+port(
+	-- control
+	operation:			in	std_logic_vector(4 downto 0);
+
+	-- operands
+	primary_operand:	in	std_logic_vector(7 downto 0);
+	secondary_operand:	in	std_logic_vector(7 downto 0);
+	flags_in:			in	std_logic_vector(7 downto 0);
+
+	--	results
+	output, flags_out:	out	std_logic_vector(7 downto 0);
+	secondary_out:		out	std_logic_vector(7 downto 0)
+);
+end;
+
+-- Tested 2016/11/22, works on Modelsim simulator along with all components.
+
+architecture struct_alu of alu is
+component bmtc is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component srl8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component sll8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component sra8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component sla8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component in_rc_flags is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component ccf_operation is
+port(
+	flags_in:	in	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component cpl is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component xor8bit is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component or8bit is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component and8bit is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component subtractor8x2 is
+port(
+	minuend, subtrahend:	in	std_logic_vector(7 downto 0);
+	borrow_in:				in	std_logic;
+	difference:				out	std_logic_vector(7 downto 0);
+	flags_out:				out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component adder8x2 is
+port(
+	addend, augend:		in	std_logic_vector(7 downto 0);
+	carry_in:			in	std_logic;
+	sum:				out	std_logic_vector(7 downto 0);
+	flags_out:			out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component magnitudeN is
+generic(
+	N:	positive
+);
+port(
+	a:		in	std_logic_vector((N-1) downto 0);
+	b:		in	std_logic_vector((N-1) downto 0);
+	equal:	out	std_logic;
+	lt:		out	std_logic; 	-- '1' if a < b
+	gt:		out	std_logic	-- '1' if a > b
+);
+end component;
+
+component rrd is
+port(
+	primary_op:			in	std_logic_vector(7 downto 0);
+	secondary_op:		in	std_logic_vector(7 downto 0);
+	result:				out	std_logic_vector(7 downto 0);
+	secondary_result:	out	std_logic_vector(7 downto 0);
+	flags_out:			out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component rld is
+port(
+	primary_op:			in	std_logic_vector(7 downto 0);
+	secondary_op:		in	std_logic_vector(7 downto 0);
+	result:				out	std_logic_vector(7 downto 0);
+	secondary_result:	out	std_logic_vector(7 downto 0);
+	flags_out:			out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component rlc8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component rl8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	carry_in:	in	std_logic;
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component rrc8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component rr8bit is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	carry_in:	in	std_logic;
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component daa is
+port(
+	operand:	in	std_logic_vector(7 downto 0);
+	flags_in:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component bit_op is
+port(
+	operand1:	in	std_logic_vector(7 downto 0);
+	operand2:	in	std_logic_vector(7 downto 0);
+	flags_out:	out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component encoder32xN is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	data2:		in	std_logic_vector((N-1) downto 0);
+	data3:		in	std_logic_vector((N-1) downto 0);
+	data4:		in	std_logic_vector((N-1) downto 0);
+	data5:		in	std_logic_vector((N-1) downto 0);
+	data6:		in	std_logic_vector((N-1) downto 0);
+	data7:		in	std_logic_vector((N-1) downto 0);
+	data8:		in	std_logic_vector((N-1) downto 0);
+	data9:		in	std_logic_vector((N-1) downto 0);
+	data10:		in	std_logic_vector((N-1) downto 0);
+	data11:		in	std_logic_vector((N-1) downto 0);
+	data12:		in	std_logic_vector((N-1) downto 0);
+	data13:		in	std_logic_vector((N-1) downto 0);
+	data14:		in	std_logic_vector((N-1) downto 0);
+	data15:		in	std_logic_vector((N-1) downto 0);
+	data16:		in	std_logic_vector((N-1) downto 0);
+	data17:		in	std_logic_vector((N-1) downto 0);
+	data18:		in	std_logic_vector((N-1) downto 0);
+	data19:		in	std_logic_vector((N-1) downto 0);
+	data20:		in	std_logic_vector((N-1) downto 0);
+	data21:		in	std_logic_vector((N-1) downto 0);
+	data22:		in	std_logic_vector((N-1) downto 0);
+	data23:		in	std_logic_vector((N-1) downto 0);
+	data24:		in	std_logic_vector((N-1) downto 0);
+	data25:		in	std_logic_vector((N-1) downto 0);
+	data26:		in	std_logic_vector((N-1) downto 0);
+	data27:		in	std_logic_vector((N-1) downto 0);
+	data28:		in	std_logic_vector((N-1) downto 0);
+	data29:		in	std_logic_vector((N-1) downto 0);
+	data30:		in	std_logic_vector((N-1) downto 0);
+	data31:		in	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(4 downto 0);
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end component;
+
+component encoder2xN_oe is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	selector:	in	std_logic;
+	enable:		in	std_logic;
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end component;
+
+signal	add_result:				std_logic_vector(7 downto 0);
+signal	add_carry_in:			std_logic;
+signal	add_flags:				std_logic_vector(7 downto 0);
+
+signal	and_result:				std_logic_vector(7 downto 0);
+signal	and_flags:				std_logic_vector(7 downto 0);
+
+signal	or_result:				std_logic_vector(7 downto 0);
+signal	or_flags:				std_logic_vector(7 downto 0);
+
+signal	xor_result:				std_logic_vector(7 downto 0);
+signal	xor_flags:				std_logic_vector(7 downto 0);
+
+signal	cpl_result:				std_logic_vector(7 downto 0);
+signal	cpl_flags:				std_logic_vector(7 downto 0);
+
+signal	subtract_result:		std_logic_vector(7 downto 0);
+signal	subtract_borrow_in:		std_logic;
+signal	subtract_flags:			std_logic_vector(7 downto 0);
+
+signal	rlc_result:				std_logic_vector(7 downto 0);
+signal	rlc_flags:				std_logic_vector(7 downto 0);
+
+signal	rrc_result:				std_logic_vector(7 downto 0);
+signal	rrc_flags:				std_logic_vector(7 downto 0);
+
+signal	rl_result:				std_logic_vector(7 downto 0);
+signal	rl_flags:				std_logic_vector(7 downto 0);
+
+signal	rr_result:				std_logic_vector(7 downto 0);
+signal	rr_flags:				std_logic_vector(7 downto 0);
+
+signal	daa_result:				std_logic_vector(7 downto 0);
+signal	daa_flags:				std_logic_vector(7 downto 0);
+
+signal	scf_flags:				std_logic_vector(7 downto 0);
+
+signal	ccf_carry:				std_logic;
+signal	ccf_flags:				std_logic_vector(7 downto 0);
+
+signal	bit_zero:				std_logic;
+signal	bit_flags:				std_logic_vector(7 downto 0);
+
+signal	in_flags:				std_logic_vector(7 downto 0);	-- flags for IN r, C instruction
+
+signal	secondary_out_enable:	std_logic;						-- '1' when executing a rrd/rld
+																-- instruction
+
+signal	rld_result:				std_logic_vector(7 downto 0);
+signal	secondary_rld_result:	std_logic_vector(7 downto 0);
+signal	rld_flags:				std_logic_vector(7 downto 0);
+signal	is_rld:					std_logic;
+
+signal	rrd_result:				std_logic_vector(7 downto 0);
+signal	secondary_rrd_result:	std_logic_vector(7 downto 0);
+signal	rrd_flags:				std_logic_vector(7 downto 0);
+signal	is_rrd:					std_logic;
+
+signal	sla_result:				std_logic_vector(7 downto 0);
+signal	sla_flags:				std_logic_vector(7 downto 0);
+
+signal	sra_result:				std_logic_vector(7 downto 0);
+signal	sra_flags:				std_logic_vector(7 downto 0);
+
+signal	sll_result:				std_logic_vector(7 downto 0);
+signal	sll_flags:				std_logic_vector(7 downto 0);
+
+signal	srl_result:				std_logic_vector(7 downto 0);
+signal	srl_flags:				std_logic_vector(7 downto 0);
+
+signal	bmtc_result:			std_logic_vector(7 downto 0);
+signal	bmtc_flags:				std_logic_vector(7 downto 0);	-- block move termination criterion
+																-- flags
+
+begin
+	-- result multiplexer, 32x8
+	u1: encoder32xN
+			generic map(
+			N => 8
+			)
+			port map(
+			data0 => add_result,								-- add, ignore carry bit
+			data1 => add_result,								-- add, add carry bit
+			data2 => subtract_result,							-- sub, ignore borrow bit
+			data3 => subtract_result, 							-- sub, subtract borrow bit
+			data4 => and_result,								-- and
+			data5 => xor_result,								-- xor
+			data6 => or_result,									-- or
+			data7 => subtract_result,							-- compare (no-borrow sub with result
+																-- discarded, used to set flags)
+			data8 => rlc_result,								-- RLC
+			data9 => rrc_result,								-- RRC
+			data10 => rl_result,								-- RL
+			data11 => rr_result,								-- RR
+			data12 => daa_result,								-- DAA
+			data13 => cpl_result,								-- CPL
+			data14 => primary_operand,							-- SCF
+			data15 => primary_operand,							-- CCF
+			data16 => sla_result,								-- SLA
+			data17 => sra_result,								-- SRA
+			data18 => sll_result,								-- SLL
+			data19 => srl_result,								-- SRL
+			data20 => secondary_operand,						-- BIT
+			data21 => and_result,								-- RES
+			data22 => or_result,								-- SET
+			data23 => primary_operand,							-- IN r, (C)
+			data24 => rld_result,								-- RLD
+			data25 => rrd_result,								-- RRD
+			data26 => bmtc_result,								-- block move termination criterion
+			data27 => (others => '0'),							-- reserved
+			data28 => (others => '0'),							-- reserved
+			data29 => (others => '0'),							-- reserved
+			data30 => (others => '0'),							-- reserved
+			data31 => (others => '0'),							-- reserved
+			address => operation,
+			output => output
+		);
+
+	-- result flags multiplexer
+	u2: encoder32xN
+			generic map(
+			N => 8
+			)
+			port map(
+			data0 => add_flags,								-- add
+			data1 => add_flags,								-- adc
+			data2 => subtract_flags,						-- sub
+			data3 => subtract_flags,						-- sbc
+			data4 => and_flags,								-- and
+			data5 => xor_flags,								-- xor
+			data6 => or_flags,								-- or
+			data7 => subtract_flags,						-- cmp
+			data8 => rlc_flags,								-- rlc
+			data9 => rrc_flags,								-- rrc
+			data10 => rl_flags,								-- rl
+			data11 => rr_flags,								-- rr
+			data12 => daa_flags,							-- daa
+			data13 => cpl_flags,							-- cpl
+			data14 => scf_flags,							-- scf
+			data15 => ccf_flags,							-- ccf
+			data16 => sla_flags,							-- SLA
+			data17 => sra_flags,							-- SRA
+			data18 => sll_flags,							-- SLL
+			data19 => srl_flags,							-- SRL
+			data20 => bit_flags,							-- BIT
+			data21 => (others => '0'),						-- RES, no flags affected
+			data22 => (others => '0'),						-- SET, no flags affected
+			data23 => in_flags,								-- IN r, (C)
+			data24 => rld_flags,							-- RLD
+			data25 => rrd_flags,							-- RRD
+			data26 => bmtc_flags,							-- block move termination criterion
+			data27 => (others => '0'),						-- reserved
+			data28 => (others => '0'),						-- reserved
+			data29 => (others => '0'),						-- reserved
+			data30 => (others => '0'),						-- reserved
+			data31 => (others => '0'),						-- reserved
+			address => operation,
+			output => flags_out
+		);
+
+	scf_flags <= (carry_bit => '1', others => '0');
+
+	-- adder: This version gets flagged by ModelSim on the carry_in line as an error.  Only signals or
+	-- maybe variables are allowed. Expressions are not.
+--	u3: adder8x2 port map(
+--			addend => primary_operand,
+--			augend => secondary_operand,
+--			carry_in => (flags_in(carry_bit) and operation(0)),	-- carry only with adc opcode, others
+--																-- made irrelevant by result mux
+--			sum => add_result,
+--			carry_out => carry_out,
+--			overflow => add_overflow,
+--			interdigit_carry => interdigit_carry,
+--			zero => add_zero
+--		);
+
+	-- adder
+	u3: adder8x2 port map(
+			addend => primary_operand,
+			augend => secondary_operand,
+			carry_in => add_carry_in,
+			sum => add_result,
+			flags_out => add_flags
+		);
+
+	add_carry_in <= flags_in(carry_bit) and operation(0);	-- carry only with adc opcode, others made
+															-- irrelevant by result mux
+
+	-- subtractor
+	u4: subtractor8x2 port map(
+			minuend => primary_operand,
+			subtrahend => secondary_operand,
+			borrow_in => subtract_borrow_in,
+			difference => subtract_result,
+			flags_out => subtract_flags
+		);
+
+	-- borrow only with sbc opcode, must remove compare opcode (operation(2 downto 0) = "111"), others
+	-- made irrelevant by result mux
+	subtract_borrow_in <= flags_in(carry_bit) and (not operation(2)) and operation(1) and operation(0);
+
+	-- bitwise and operation
+	u5: and8bit port map(
+			operand1 => primary_operand,
+			operand2 => secondary_operand,
+			output => and_result,
+			flags_out => and_flags
+		);
+
+	-- bitwise exclusive-or operation
+	u6: xor8bit port map(
+			operand1 => primary_operand,
+			operand2 => secondary_operand,
+			output => xor_result,
+			flags_out => xor_flags
+		);
+
+	-- bitwise or operation
+	u7: or8bit port map(
+			operand1 => primary_operand,
+			operand2 => secondary_operand,
+			output => or_result,
+			flags_out => or_flags
+		);
+
+	-- RLC generator
+	u8:	rlc8bit port map(
+			operand => primary_operand,
+			output => rlc_result,
+			flags_out => rlc_flags
+		);
+
+	-- RRC generator
+	u9:	rrc8bit port map(
+			operand => primary_operand,
+			output => rrc_result,
+			flags_out => rrc_flags
+		);
+
+	-- RL generator
+	u10: rl8bit port map(
+			operand => primary_operand,
+			carry_in => flags_in(carry_bit),
+			output => rl_result,
+			flags_out => rl_flags
+		);
+
+	-- RR generator
+	u11: rr8bit port map(
+			operand => primary_operand,
+			carry_in => flags_in(carry_bit),
+			output => rr_result,
+			flags_out => rr_flags
+		);
+
+	-- DAA
+	u12: daa port map(
+			operand => primary_operand,
+			flags_in => flags_in,
+			output => daa_result,
+			flags_out => daa_flags
+		);
+
+	-- bit testing of secondary operand against mask in primary operand
+	u13: bit_op port map(
+		 	operand1 => primary_operand,
+			operand2 => secondary_operand,
+			flags_out => bit_flags
+		);
+
+	u14: rld port map(
+			primary_op => primary_operand,
+			secondary_op => secondary_operand,
+			result => rld_result,
+			secondary_result => secondary_rld_result,
+			flags_out => rld_flags
+		);
+
+	u15: magnitudeN
+			generic map(
+				N => 5
+			)
+			port map(
+			a => operation,
+			b => rrd_operation,
+			equal => is_rrd,
+			lt => open,
+			gt => open
+		);
+
+	u16: magnitudeN
+			generic map(
+				N => 5
+			)
+			port map(
+			a => operation,
+			b => rld_operation,
+			equal => is_rld,
+			lt => open,
+			gt => open
+		);
+
+	u17: rrd port map(
+			primary_op => primary_operand,
+			secondary_op => secondary_operand,
+			result => rrd_result,
+			secondary_result => secondary_rrd_result,
+			flags_out => rrd_flags
+		);
+
+	u18: encoder2xN_oe
+			generic map(
+			N => 8
+			)
+			port map(
+			data0 => secondary_rld_result,
+			data1 => secondary_rrd_result,
+			selector => is_rrd,
+			enable => secondary_out_enable,
+			output => secondary_out
+		);
+
+	secondary_out_enable <= is_rrd or is_rld;
+
+	u19: cpl port map(
+			operand => primary_operand,
+			output => cpl_result,
+			flags_out => cpl_flags
+		);
+
+	u20: ccf_operation port map(
+			flags_in => flags_in,
+			flags_out => ccf_flags
+		);
+
+	u21: in_rc_flags port map(
+			operand => primary_operand,
+			flags_out => in_flags
+		);
+
+	u22: sla8bit port map(
+			operand => primary_operand,
+			output => sla_result,
+			flags_out => sla_flags
+		);
+
+	u23: sra8bit port map(
+			operand => primary_operand,
+			output => sra_result,
+			flags_out => sra_flags
+		);
+
+	u24: sll8bit port map(
+			operand => primary_operand,
+			output => sll_result,
+			flags_out => sll_flags
+		);
+
+	u25: srl8bit port map(
+			operand => primary_operand,
+			output => srl_result,
+			flags_out => srl_flags
+		);
+
+	u26: bmtc port map(
+			operand1 => primary_operand,
+			operand2 => secondary_operand,
+			output => bmtc_result,
+			flags_out => bmtc_flags
+		);
+end;
diff --git a/testsuite/gna/issue30/basicblocks.vhdl b/testsuite/gna/issue30/basicblocks.vhdl
new file mode 100644
index 000000000..e21a9ff04
--- /dev/null
+++ b/testsuite/gna/issue30/basicblocks.vhdl
@@ -0,0 +1,6992 @@
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+package basicblocks_definitions is
+constant	period:			time := 10 ns;
+constant	half_period:	time := period / 2;
+constant	reset_time:		time := 11 ns;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+library	work;
+use		work.basicblocks_definitions.all;
+
+-- FOR SIMULATION ONLY. NOT FOR PRODUCTION.
+
+entity clkgen is
+port(
+	clk_out:	out	std_logic;
+	resetn:		out	std_logic := '0'
+);
+end;
+
+-- Tested 2016/01/19 with ghdl.  works.
+
+architecture struct_clkgen of clkgen is
+
+begin
+	process begin
+
+		resetn <= '1' after reset_time;
+
+		clk_out <= '1';
+		wait for half_period;
+
+		clk_out <= '0';
+		wait for half_period;
+	end process;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity incrementer is
+port(
+	input:		in	std_logic;
+	carry_in:	in	std_logic;
+	sum:		out	std_logic;
+	carry_out:	out	std_logic
+);
+end;
+
+-- tested with ghdl for N = 16 starting 2016/01/22, finished ?, works.
+
+architecture struct_incrementer of incrementer is
+begin
+	sum <= input xor carry_in;
+	carry_out <= input and carry_in;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity andNbit is
+generic(
+	N:	positive
+);
+port(
+	input:	in	std_logic_vector((N-1) downto 0);
+	y:		out	std_logic
+);
+end;
+
+-- Tested as part of counter testing.  Works.
+
+architecture struct_andNbit of andNbit is
+
+signal	and_vector:	std_logic_vector(N downto 0);
+
+begin
+	and_vector(0) <= '1';
+
+	and_generator:
+		for i in 1 to N generate
+		and_vector(i) <= and_vector(i-1) and input(i-1);
+	end generate and_generator;
+
+	y <= and_vector(N);
+
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity orNbit is
+generic(
+	N:	positive
+);
+port(
+	input:	in	std_logic_vector((N-1) downto 0);
+	y:		out	std_logic
+);
+end;
+
+architecture struct_orNbit of orNbit is
+
+signal	or_vector:	std_logic_vector(N downto 0);
+
+begin
+	or_vector(0) <= '0';
+
+	or_generator:
+		for i in 1 to N generate
+		or_vector(i) <= or_vector(i-1) or input(i-1);
+	end generate or_generator;
+
+	y <= or_vector(N);
+
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity incrementerN is
+generic(
+	N:	positive
+);
+port(
+	input:		in	std_logic_vector((N-1) downto 0);
+	carry_in:	in	std_logic;
+	sum:		out	std_logic_vector((N-1) downto 0);
+	carry_out:	out	std_logic
+);
+end;
+
+-- tested with ghdl at N = 16 starting 2016/01/22, finished ?, works.
+
+architecture struct_incrementerN of incrementerN is
+component incrementer is
+port(
+	input:		in	std_logic;
+	carry_in:	in	std_logic;
+	sum:		out	std_logic;
+	carry_out:	out	std_logic
+);
+end component;
+
+signal	carry:	std_logic_vector(N downto 0);
+signal	result:	std_logic_vector((N-1) downto 0);
+
+begin
+	carry(0) <= carry_in;
+
+	u1: for i in (N-1) downto 0 generate
+		u: incrementer port map(
+			input => input(i),
+			carry_in => carry(i),
+			sum => result(i),
+			carry_out => carry(i + 1)
+		);
+	end generate;
+
+	carry_out <= carry(N);
+	sum <= result;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity decoder1x16 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	address:	in	std_logic_vector(3 downto 0)
+);
+end;
+
+architecture struct_decoder1x16 of decoder1x16 is
+begin
+	with address select	y0	<= data when x"0", '0' when others;
+	with address select	y1	<= data when x"1", '0' when others;
+	with address select	y2	<= data when x"2", '0' when others;
+	with address select	y3	<= data when x"3", '0' when others;
+	with address select	y4	<= data when x"4", '0' when others;
+	with address select	y5	<= data when x"5", '0' when others;
+	with address select	y6	<= data when x"6", '0' when others;
+	with address select	y7	<= data when x"7", '0' when others;
+	with address select	y8	<= data when x"8", '0' when others;
+	with address select	y9	<= data when x"9", '0' when others;
+	with address select	y10	<= data when x"a", '0' when others;
+	with address select	y11	<= data when x"b", '0' when others;
+	with address select	y12	<= data when x"c", '0' when others;
+	with address select	y13	<= data when x"d", '0' when others;
+	with address select	y14	<= data when x"e", '0' when others;
+	with address select	y15	<= data when x"f", '0' when others;
+end;
+
+-- For reasons unknown, ghdl appears to ignore the generic definition of N in this and only
+-- this architecture.  Error messages are generated at line 129 onwards.  No unusual characters
+-- found in the file where the first error message is generated.
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity decoderNx16 is
+generic(
+	N:	positive
+);
+port(
+	data:		in	std_logic_vector((N-1) downto 0);
+	y0:			out	std_logic_vector((N-1) downto 0);
+	y1:			out	std_logic_vector((N-1) downto 0);
+	y2:			out	std_logic_vector((N-1) downto 0);
+	y3:			out	std_logic_vector((N-1) downto 0);
+	y4:			out	std_logic_vector((N-1) downto 0);
+	y5:			out	std_logic_vector((N-1) downto 0);
+	y6:			out	std_logic_vector((N-1) downto 0);
+	y7:			out	std_logic_vector((N-1) downto 0);
+	y8:			out	std_logic_vector((N-1) downto 0);
+	y9:			out	std_logic_vector((N-1) downto 0);
+	y10:		out	std_logic_vector((N-1) downto 0);
+	y11:		out	std_logic_vector((N-1) downto 0);
+	y12:		out	std_logic_vector((N-1) downto 0);
+	y13:		out	std_logic_vector((N-1) downto 0);
+	y14:		out	std_logic_vector((N-1) downto 0);
+	y15:		out	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(3 downto 0)
+);
+end;
+
+architecture struct_decoderNx16 of decoderNx16 is
+component decoder1x16 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	address:	in	std_logic_vector(3 downto 0)
+);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: decoder1x16 port map(
+			data => data(i),
+			y0	=> y0(i),
+			y1	=> y1(i),
+			y2	=> y2(i),
+			y3	=> y3(i),
+			y4	=> y4(i),
+			y5	=> y5(i),
+			y6	=> y6(i),
+			y7	=> y7(i),
+			y8	=> y8(i),
+			y9	=> y9(i),
+			y10	=> y10(i),
+			y11	=> y11(i),
+			y12	=> y12(i),
+			y13	=> y13(i),
+			y14	=> y14(i),
+			y15	=> y15(i),
+			address => address
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity decoder1x2 is
+port(
+	data:		in	std_logic;
+	selector:	in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic
+);
+end;
+
+-- Tested 2015/12/04 with Modelsim.  Works.
+
+architecture struct_decoder1x2 of decoder1x2 is
+begin
+	with selector select y0 <= data when '0', '0' when others;
+	with selector select y1 <= data when '1', '0' when others;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity decoderNx2 is
+generic(
+	N: positive
+);
+port(
+	data:		in	std_logic_vector((N-1) downto 0);
+	selector:	in	std_logic;
+	y0:			out	std_logic_vector((N-1) downto 0);
+	y1:			out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- tested 2015/12/27 at N = 8 with modelsim.  works.
+-- tested 2016/01/23 at N = 8 with ghdl. works.
+
+architecture struct_decoderNx2 of decoderNx2 is
+component decoder1x2 is
+port(
+	data:		in	std_logic;
+	selector:	in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic
+);
+end component;
+
+begin
+	u1:	for i in (N-1) downto 0 generate
+		u: decoder1x2 port map(
+			data => data(i),
+			selector => selector,
+			y0 => y0(i),
+			y1 => y1(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder2x1oe is
+port(
+	data0, data1:	in	std_logic;
+	selector:		in	std_logic;
+	enable:			in	std_logic;
+	output:			out	std_logic
+);
+end;
+
+-- tested during testing of encoder2xNoe, works.
+
+architecture struct_encoder2x1oe of encoder2x1oe is
+begin
+	with selector select
+		output <=	(data0 and enable) when '0',
+					(data1 and enable) when '1',
+					'0' when others;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder2xN_oe is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	selector:	in	std_logic;
+	enable:		in	std_logic;
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+architecture struct_encoder2xN_oe of encoder2xN_oe is
+component encoder2x1oe is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	selector:	in	std_logic;
+	enable:		in	std_logic;
+	output:		out	std_logic
+);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: encoder2x1oe port map(
+			data0 => data0(i),
+			data1 => data1(i),
+			selector => selector,
+			enable => enable,
+			output => output(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder2x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	selector:	in	std_logic;
+	output:		out	std_logic
+);
+end;
+
+-- tested during double register pair testing 2015/12/03.  Works.
+
+architecture struct_encoder2x1 of encoder2x1 is
+begin
+	with selector select
+		output <=	data0 when '0',
+					data1 when '1',
+					'0' when others;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder2xN is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	selector:	in	std_logic;
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- tested during double register pair testing 2015/12/03.  Works for N = 8.
+-- also tested during alu testing.  works there too.
+
+architecture struct_encoder2xN of encoder2xN is
+component encoder2x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	selector:	in	std_logic;
+	output:		out	std_logic
+);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: encoder2x1 port map(
+			data0 => data0(i),
+			data1 => data1(i),
+			selector => selector,
+			output => output(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity synchronous_latch is
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic;
+	q:				out	std_logic
+);
+end;
+
+-- Tested 2016/11/21, works on Modelsim simulator.
+
+architecture struct_synchronous_latch of synchronous_latch is
+begin
+	process(rstn, clock, clock_enable)
+	variable	datum:	std_logic;
+	begin
+		if rstn = '0' then
+			datum := '0';
+		elsif rising_edge(clock) then
+			if clock_enable = '1' then
+				datum := d;
+			end if;
+		end if;
+
+		q <= datum;
+	end process;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+-- library	altera;
+-- use		altera.altera_primitives_components.all;
+
+entity synchronous_latchN is
+generic(
+	N:	positive
+);
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic_vector((N-1) downto 0);
+	q:				out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- Tested 2016/11/21, works on Modelsim simulator.
+
+architecture struct_synchronous_latchN of synchronous_latchN is
+component synchronous_latch is
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic;
+	q:				out	std_logic
+);
+end component;
+
+begin
+	u1:	for i in 0 to (N-1) generate
+		u: synchronous_latch port map(
+			rstn => rstn,
+			clock => clock,
+			clock_enable => clock_enable,
+			d => d(i),
+			q => q(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity synchronous_latch_oe is
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	oe:				in	std_logic;
+	d:				in	std_logic;
+	q:				out	std_logic
+);
+end;
+
+-- tested 2015/12/27 as part of testing synchronous_latchN_oe.  works.
+
+architecture struct_synchronous_latch_oe of synchronous_latch_oe is
+begin
+	process(rstn, clock, clock_enable, oe)
+	variable	datum:	std_logic;
+	begin
+		if rstn = '0' then
+			datum := '0';
+		elsif rising_edge(clock) then
+			if clock_enable = '1' then
+				datum := d;
+			end if;
+		end if;
+
+		if oe = '1' then
+			q <= datum;
+		else
+			q <= 'Z';
+		end if;
+	end process;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity synchronous_latchN_oe is
+generic(
+	N: positive
+);
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	oe:				in	std_logic;
+	d:				in	std_logic_vector((N-1) downto 0);
+	q:				out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- tested 2015/12/27, N = 8 with modelsim.  works.
+
+architecture struct_synchronous_latchN_oe of synchronous_latchN_oe is
+component synchronous_latch_oe is
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	oe:				in	std_logic;
+	d:				in	std_logic;
+	q:				out	std_logic
+);
+end component;
+
+begin
+	u1:	for i in (N-1) downto 0 generate
+		u: synchronous_latch_oe port map(
+			rstn => rstn,
+			clock => clock,
+			clock_enable => clock_enable,
+			oe => oe,
+			d => d(i),
+			q => q(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity synchronous_latch_autoclear is
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic;
+	q:				out	std_logic
+);
+end;
+
+-- Tested 2016/11/21, works on Modelsim simulator.
+
+architecture struct_synchronous_latch_autoclear of synchronous_latch_autoclear is
+begin
+	process(rstn, clock)
+	variable	datum:	std_logic;
+	begin
+		if rstn = '0' then
+			datum := '0';
+		elsif rising_edge(clock) then
+			if clock_enable = '1' then
+				if datum = '1' then
+					datum := '0';
+				else
+					datum := d;
+				end if;
+			else
+				datum := '0';
+			end if;
+		end if;
+
+		q <= datum;
+	end process;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder4x1 is
+port(
+	data0:		in  std_logic;
+	data1:		in  std_logic;
+	data2:		in  std_logic;
+	data3:		in  std_logic;
+	address:	in  std_logic_vector(1 downto 0);
+	output:		out std_logic
+	);
+end;
+
+-- tested 2015/12/26 with modelsim as part of encoder4xN, works.
+
+architecture struct_encoder4x1 of encoder4x1 is
+begin
+	with address select
+		output <=	data0 when "00",
+					data1 when "01",
+					data2 when "10",
+					data3 when "11",
+					'0' when others;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder4xN is
+generic(
+	N:	positive
+);
+port(
+	data0:		in  std_logic_vector((N-1) downto 0);
+	data1:		in  std_logic_vector((N-1) downto 0);
+	data2:		in  std_logic_vector((N-1) downto 0);
+	data3:		in  std_logic_vector((N-1) downto 0);
+	address:	in  std_logic_vector(1 downto 0);
+	output:		out std_logic_vector((N-1) downto 0)
+	);
+end;
+
+-- tested 2015/12/26 with modelsim at N = 16, works.
+
+architecture struct_encoder4xN of encoder4xN is
+component encoder4x1 is
+port(
+	data0:		in  std_logic;
+	data1:		in  std_logic;
+	data2:		in  std_logic;
+	data3:		in  std_logic;
+	address:	in  std_logic_vector(1 downto 0);
+	output:		out std_logic
+	);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: encoder4x1 port map(
+			data0 => data0(i),
+			data1 => data1(i),
+			data2 => data2(i),
+			data3 => data3(i),
+			address => address,
+			output => output(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder8x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	address:	in	std_logic_vector(2 downto 0);
+	output:		out	std_logic
+);
+end;
+
+-- tested 2015/12/26 as part of encoder8xN with modelsim, works.
+
+architecture struct_encoder8x1 of encoder8x1 is
+begin
+	with address select
+		output <=	data0 when "000",
+					data1 when "001",
+					data2 when "010",
+					data3 when "011",
+					data4 when "100",
+					data5 when "101",
+					data6 when "110",
+					data7 when "111",
+					'0' when others;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder8xN is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	data2:		in	std_logic_vector((N-1) downto 0);
+	data3:		in	std_logic_vector((N-1) downto 0);
+	data4:		in	std_logic_vector((N-1) downto 0);
+	data5:		in	std_logic_vector((N-1) downto 0);
+	data6:		in	std_logic_vector((N-1) downto 0);
+	data7:		in	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(2 downto 0);
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- tested 2015/12/26 for N = 8 with modelsim, works.
+
+architecture struct_encoder8xN of encoder8xN is
+component encoder8x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	address:	in	std_logic_vector(2 downto 0);
+	output:		out	std_logic
+);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: encoder8x1 port map(
+			data0 => data0(i),
+			data1 => data1(i),
+			data2 => data2(i),
+			data3 => data3(i),
+			data4 => data4(i),
+			data5 => data5(i),
+			data6 => data6(i),
+			data7 => data7(i),
+			address => address,
+			output => output(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity decoder1x8 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	address:	in	std_logic_vector(2 downto 0)
+);
+end;
+
+-- tested 2015/12/30 with modelsim as part of decoderNx8, works.
+
+architecture struct_decoder1x8 of decoder1x8 is
+begin
+	with address select y0	<= data when "000", '0' when others;
+	with address select y1	<= data when "001", '0' when others;
+	with address select y2	<= data when "010", '0' when others;
+	with address select y3	<= data when "011", '0' when others;
+	with address select y4	<= data when "100", '0' when others;
+	with address select y5	<= data when "101", '0' when others;
+	with address select y6	<= data when "110", '0' when others;
+	with address select y7	<= data when "111", '0' when others;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity decoderNx8 is
+generic(
+	N:	positive
+);
+port(
+	data:		in	std_logic_vector((N-1) downto 0);
+	y0:			out	std_logic_vector((N-1) downto 0);
+	y1:			out	std_logic_vector((N-1) downto 0);
+	y2:			out	std_logic_vector((N-1) downto 0);
+	y3:			out	std_logic_vector((N-1) downto 0);
+	y4:			out	std_logic_vector((N-1) downto 0);
+	y5:			out	std_logic_vector((N-1) downto 0);
+	y6:			out	std_logic_vector((N-1) downto 0);
+	y7:			out	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(2 downto 0)
+);
+end;
+
+-- tested 2015/12/30 with modelsim, works.
+
+architecture struct_decoderNx8 of decoderNx8 is
+component decoder1x8 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	address:	in	std_logic_vector(2 downto 0)
+);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: decoder1x8 port map(
+			data => data(i),
+			y0	=> y0(i),
+			y1	=> y1(i),
+			y2	=> y2(i),
+			y3	=> y3(i),
+			y4	=> y4(i),
+			y5	=> y5(i),
+			y6	=> y6(i),
+			y7	=> y7(i),
+			address=> address
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder16x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	data8:		in	std_logic;
+	data9:		in	std_logic;
+	data10:		in	std_logic;
+	data11:		in	std_logic;
+	data12:		in	std_logic;
+	data13:		in	std_logic;
+	data14:		in	std_logic;
+	data15:		in	std_logic;
+	address:	in	std_logic_vector(3 downto 0);
+	output:		out	std_logic
+);
+end;
+
+-- tested with Modelsim 2015/12/24 as part of encoder16xN, works with N = 8.
+
+architecture struct_encoder16x1 of encoder16x1 is
+begin
+	with address select
+		output <=	data0	when	"0000",
+					data1	when	"0001",
+					data2	when	"0010",
+					data3	when	"0011",
+					data4	when	"0100",
+					data5	when	"0101",
+					data6	when	"0110",
+					data7	when	"0111",
+					data8	when	"1000",
+					data9	when	"1001",
+					data10	when	"1010",
+					data11	when	"1011",
+					data12	when	"1100",
+					data13	when	"1101",
+					data14	when	"1110",
+					data15	when	"1111",
+					'0' when others;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder16xN is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	data2:		in	std_logic_vector((N-1) downto 0);
+	data3:		in	std_logic_vector((N-1) downto 0);
+	data4:		in	std_logic_vector((N-1) downto 0);
+	data5:		in	std_logic_vector((N-1) downto 0);
+	data6:		in	std_logic_vector((N-1) downto 0);
+	data7:		in	std_logic_vector((N-1) downto 0);
+	data8:		in	std_logic_vector((N-1) downto 0);
+	data9:		in	std_logic_vector((N-1) downto 0);
+	data10:		in	std_logic_vector((N-1) downto 0);
+	data11:		in	std_logic_vector((N-1) downto 0);
+	data12:		in	std_logic_vector((N-1) downto 0);
+	data13:		in	std_logic_vector((N-1) downto 0);
+	data14:		in	std_logic_vector((N-1) downto 0);
+	data15:		in	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(3 downto 0);
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- tested with Modelsim 2015/12/24, works with N = 8.
+
+architecture struct_encoder16xN of encoder16xN is
+component encoder16x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	data8:		in	std_logic;
+	data9:		in	std_logic;
+	data10:		in	std_logic;
+	data11:		in	std_logic;
+	data12:		in	std_logic;
+	data13:		in	std_logic;
+	data14:		in	std_logic;
+	data15:		in	std_logic;
+	address:	in	std_logic_vector(3 downto 0);
+	output:		out	std_logic
+);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: encoder16x1 port map(
+				data0 => data0(i),
+				data1 => data1(i),
+				data2 => data2(i),
+				data3 => data3(i),
+				data4 => data4(i),
+				data5 => data5(i),
+				data6 => data6(i),
+				data7 => data7(i),
+				data8 => data8(i),
+				data9 => data9(i),
+				data10 => data10(i),
+				data11 => data11(i),
+				data12 => data12(i),
+				data13 => data13(i),
+				data14 => data14(i),
+				data15 => data15(i),
+				address => address,
+				output => output(i)
+			);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder32x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	data8:		in	std_logic;
+	data9:		in	std_logic;
+	data10:		in	std_logic;
+	data11:		in	std_logic;
+	data12:		in	std_logic;
+	data13:		in	std_logic;
+	data14:		in	std_logic;
+	data15:		in	std_logic;
+	data16:		in	std_logic;
+	data17:		in	std_logic;
+	data18:		in	std_logic;
+	data19:		in	std_logic;
+	data20:		in	std_logic;
+	data21:		in	std_logic;
+	data22:		in	std_logic;
+	data23:		in	std_logic;
+	data24:		in	std_logic;
+	data25:		in	std_logic;
+	data26:		in	std_logic;
+	data27:		in	std_logic;
+	data28:		in	std_logic;
+	data29:		in	std_logic;
+	data30:		in	std_logic;
+	data31:		in	std_logic;
+	address:	in	std_logic_vector(4 downto 0);
+	output:		out	std_logic
+);
+end;
+
+-- tested 2015/12/24 as part of testing encoder32xN.  Works.
+
+architecture struct_encoder32x1 of encoder32x1 is
+begin
+	with address select
+		output <=	data0	when	"00000",
+					data1	when	"00001",
+					data2	when	"00010",
+					data3	when	"00011",
+					data4	when	"00100",
+					data5	when	"00101",
+					data6	when	"00110",
+					data7	when	"00111",
+					data8	when	"01000",
+					data9	when	"01001",
+					data10	when	"01010",
+					data11	when	"01011",
+					data12	when	"01100",
+					data13	when	"01101",
+					data14	when	"01110",
+					data15	when	"01111",
+					data16	when	"10000",
+					data17	when	"10001",
+					data18	when	"10010",
+					data19	when	"10011",
+					data20	when	"10100",
+					data21	when	"10101",
+					data22	when	"10110",
+					data23	when	"10111",
+					data24	when	"11000",
+					data25	when	"11001",
+					data26	when	"11010",
+					data27	when	"11011",
+					data28	when	"11100",
+					data29	when	"11101",
+					data30	when	"11110",
+					data31	when	"11111",
+					'0' when others;
+end;
+
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity encoder32xN is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	data2:		in	std_logic_vector((N-1) downto 0);
+	data3:		in	std_logic_vector((N-1) downto 0);
+	data4:		in	std_logic_vector((N-1) downto 0);
+	data5:		in	std_logic_vector((N-1) downto 0);
+	data6:		in	std_logic_vector((N-1) downto 0);
+	data7:		in	std_logic_vector((N-1) downto 0);
+	data8:		in	std_logic_vector((N-1) downto 0);
+	data9:		in	std_logic_vector((N-1) downto 0);
+	data10:		in	std_logic_vector((N-1) downto 0);
+	data11:		in	std_logic_vector((N-1) downto 0);
+	data12:		in	std_logic_vector((N-1) downto 0);
+	data13:		in	std_logic_vector((N-1) downto 0);
+	data14:		in	std_logic_vector((N-1) downto 0);
+	data15:		in	std_logic_vector((N-1) downto 0);
+	data16:		in	std_logic_vector((N-1) downto 0);
+	data17:		in	std_logic_vector((N-1) downto 0);
+	data18:		in	std_logic_vector((N-1) downto 0);
+	data19:		in	std_logic_vector((N-1) downto 0);
+	data20:		in	std_logic_vector((N-1) downto 0);
+	data21:		in	std_logic_vector((N-1) downto 0);
+	data22:		in	std_logic_vector((N-1) downto 0);
+	data23:		in	std_logic_vector((N-1) downto 0);
+	data24:		in	std_logic_vector((N-1) downto 0);
+	data25:		in	std_logic_vector((N-1) downto 0);
+	data26:		in	std_logic_vector((N-1) downto 0);
+	data27:		in	std_logic_vector((N-1) downto 0);
+	data28:		in	std_logic_vector((N-1) downto 0);
+	data29:		in	std_logic_vector((N-1) downto 0);
+	data30:		in	std_logic_vector((N-1) downto 0);
+	data31:		in	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(4 downto 0);
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- tested 2015/12/24 with N = 8.  Works.
+
+architecture struct_encoder32xN of encoder32xN is
+component encoder32x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	data8:		in	std_logic;
+	data9:		in	std_logic;
+	data10:		in	std_logic;
+	data11:		in	std_logic;
+	data12:		in	std_logic;
+	data13:		in	std_logic;
+	data14:		in	std_logic;
+	data15:		in	std_logic;
+	data16:		in	std_logic;
+	data17:		in	std_logic;
+	data18:		in	std_logic;
+	data19:		in	std_logic;
+	data20:		in	std_logic;
+	data21:		in	std_logic;
+	data22:		in	std_logic;
+	data23:		in	std_logic;
+	data24:		in	std_logic;
+	data25:		in	std_logic;
+	data26:		in	std_logic;
+	data27:		in	std_logic;
+	data28:		in	std_logic;
+	data29:		in	std_logic;
+	data30:		in	std_logic;
+	data31:		in	std_logic;
+	address:	in	std_logic_vector(4 downto 0);
+	output:		out	std_logic
+);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: encoder32x1 port map(
+			data0 => data0(i),
+			data1 => data1(i),
+			data2 => data2(i),
+			data3 => data3(i),
+			data4 => data4(i),
+			data5 => data5(i),
+			data6 => data6(i),
+			data7 => data7(i),
+			data8 => data8(i),
+			data9 => data9(i),
+			data10 => data10(i),
+			data11 => data11(i),
+			data12 => data12(i),
+			data13 => data13(i),
+			data14 => data14(i),
+			data15 => data15(i),
+			data16 => data16(i),
+			data17 => data17(i),
+			data18 => data18(i),
+			data19 => data19(i),
+			data20 => data20(i),
+			data21 => data21(i),
+			data22 => data22(i),
+			data23 => data23(i),
+			data24 => data24(i),
+			data25 => data25(i),
+			data26 => data26(i),
+			data27 => data27(i),
+			data28 => data28(i),
+			data29 => data29(i),
+			data30 => data30(i),
+			data31 => data31(i),
+			address => address,
+			output => output(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity tristate is
+port(
+	a: 		in	std_logic;
+	enable:	in	std_logic;
+	y: 		out	std_logic
+);
+end;
+
+-- tested 2015/12/27 with modelsim as part of tristateN testing.  works.
+-- tested 2016/01/23 with ghdl as part of tristateN testing.  works.
+
+architecture struct_tristate of tristate is
+begin
+	y <= a when enable = '1' else 'Z';
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity tristateN is
+generic(
+	N: positive
+);
+port(
+	a: 		in	std_logic_vector((N-1) downto 0);
+	enable:	in	std_logic;
+	y: 		out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- tested 2015/12/27 at N = 16 with modelsim.  works.
+-- tested 2016/01/23 at N = 16 with ghdl.  works.
+
+architecture struct_tristateN of tristateN is
+component tristate is
+port(
+	a: 		in	std_logic;
+	enable:	in	std_logic;
+	y: 		out	std_logic
+);
+end component;
+
+begin
+	u1: for i in 0 to (N-1) generate
+		u: tristate port map(
+			a => a(i),
+			enable => enable,
+			y => y(i)
+		);
+	end generate;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity toggle_ff is
+port(
+	clk:			in	std_logic;
+	clock_enable:	in	std_logic;
+	resetn:			in	std_logic;
+	q:				out	std_logic
+);
+end;
+
+-- tested 2015/12/26 with modelsim, works.
+
+architecture struct_toggle_ff of toggle_ff is
+component synchronous_latch is
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic;
+	q:				out	std_logic
+);
+end component;
+
+component synchronous_latch_autoclear is
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic;
+	q:				out	std_logic
+);
+end component;
+
+component encoder2x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	selector:	in	std_logic;
+	output:		out	std_logic
+);
+end component;
+
+signal	toggle_output:		std_logic;
+signal	toggle_clock:		std_logic;
+signal	flipflop_data:		std_logic;
+signal	not_toggle_output:	std_logic;
+signal	notclock:			std_logic;
+
+begin
+	u1: synchronous_latch port map(
+			rstn => resetn,
+			clock => clk,
+			clock_enable => toggle_clock,
+			d => flipflop_data,
+			q => toggle_output
+		);
+
+	u2: encoder2x1 port map(
+			data0 => toggle_output,
+			data1 => not_toggle_output,
+			selector => toggle_clock,
+			output => flipflop_data
+		);
+
+	u3: synchronous_latch_autoclear port map(
+			rstn => resetn,
+			clock => notclock,
+			clock_enable => clock_enable,
+			d => clock_enable,
+			q => toggle_clock
+		);
+
+	not_toggle_output <= not toggle_output;
+	notclock <= not clk;
+	q <= toggle_output;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity magnitude is
+port(
+	a, b:	in	std_logic;
+	equal:	out	std_logic;
+	lt:		out	std_logic; 	-- '1' if a < b
+	gt:		out	std_logic	-- '1' if a > b
+);
+end;
+
+-- tested 2015/12/26 with modelsim, works.
+
+architecture struct_magnitude of magnitude is
+
+signal	equals:	std_logic;
+signal	less:	std_logic;
+
+begin
+	equals <= not (a xor b);
+	less <= (not a) and b;
+	gt <= equals nor less;
+	equal <= equals;
+	lt <= less;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity magnitudeN is
+generic(
+	N:	positive
+);
+port(
+	a, b:	in	std_logic_vector((N-1) downto 0);
+	equal:	out	std_logic;
+	lt:		out	std_logic; 	-- '1' if a < b
+	gt:		out	std_logic	-- '1' if a > b
+);
+end;
+
+--tested with ghdl 2016/01/26, works.
+
+architecture struct_magnitudeN of magnitudeN is
+
+signal	equals:	std_logic_vector((N-1) downto 0);
+signal	less:	std_logic_vector((N-1) downto 0);
+
+begin
+	equals(N-1) <= not (a(N-1) xor b(N-1));
+	less (N-1) <= (not a(N-1)) and b(N-1);
+
+	u1:	for i in (N-1) downto 1 generate
+		equals(i-1) <= equals(i) and (not (a(i-1) xor b(i-1)));
+		less(i-1) <= less(i) or (((not a(i-1)) and b(i-1)) and equals(i));
+	end generate u1;
+
+	equal <= equals(0);
+	lt <= less(0);
+	gt <= equals(0) nor less(0);
+end;
+
+
+--library	ieee;
+--use	ieee.std_logic_1164.all;
+--
+--entity magnitude2 is
+--port(
+--	a, b:	in	std_logic_vector(1 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end;
+--
+---- tested 2015/12/26 with modelsim, works.
+--
+--architecture struct_magnitude2 of magnitude2 is
+--component magnitude is
+--port(
+--	a, b:	in	std_logic;
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--signal	high_equals:	std_logic;
+--signal	high_lt:	   	std_logic;
+--signal	high_gt:		std_logic;
+--
+--signal	low_equals:		std_logic;
+--signal	low_lt:	   		std_logic;
+--signal	low_gt:			std_logic;
+--
+--signal	equals:			std_logic;
+--signal	less:			std_logic;
+--
+--begin
+--	u1: magnitude port map(
+--		a => a(1),
+--		b => b(1),
+--		equal => high_equals,
+--		lt => high_lt,
+--		gt => high_gt
+--	);
+--
+--	u2: magnitude port map(
+--		a => a(0),
+--		b => b(0),
+--		equal => low_equals,
+--		lt => low_lt,
+--		gt => low_gt
+--	);
+--
+--	equals <= high_equals and low_equals;
+--	less <= high_lt or (high_equals and low_lt);
+--	gt <= equals nor less;
+--	equal <= equals;
+--	lt <= less;
+--end;
+--
+--library	ieee;
+--use	ieee.std_logic_1164.all;
+--
+--entity magnitude3 is
+--port(
+--	a, b:	in	std_logic_vector(2 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end;
+--
+---- tested 2015/12/26 with modelsim, works.
+--
+--architecture struct_magnitude3 of magnitude3 is
+--component magnitude2 is
+--port(
+--	a, b:	in	std_logic_vector(1 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--component magnitude is
+--port(
+--	a, b:	in	std_logic;
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--signal	high_equals:	std_logic;
+--signal	high_lt:	   	std_logic;
+--signal	high_gt:		std_logic;
+--
+--signal	low_equals:		std_logic;
+--signal	low_lt:	   		std_logic;
+--signal	low_gt:			std_logic;
+--
+--signal	equals:			std_logic;
+--signal	less:			std_logic;
+--
+--begin
+--	u1: magnitude port map(
+--		a => a(2),
+--		b => b(2),
+--		equal => high_equals,
+--		lt => high_lt,
+--		gt => high_gt
+--	);
+--
+--	u2: magnitude2 port map(
+--		a => a(1 downto 0),
+--		b => b(1 downto 0),
+--		equal => low_equals,
+--		lt => low_lt,
+--		gt => low_gt
+--	);
+--
+--	equals <= high_equals and low_equals;
+--	less <= high_lt or (high_equals and low_lt);
+--	gt <= equals nor less;
+--	equal <= equals;
+--	lt <= less;
+--end;
+--
+--library	ieee;
+--use	ieee.std_logic_1164.all;
+--
+--entity magnitude4 is
+--port(
+--	a, b:	in	std_logic_vector(3 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end;
+--
+---- tested 2015/12/26 with modelsim, works.
+--
+--architecture struct_magnitude4 of magnitude4 is
+--component magnitude3 is
+--port(
+--	a, b:	in	std_logic_vector(2 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--component magnitude is
+--port(
+--	a, b:	in	std_logic;
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--signal	high_equals:	std_logic;
+--signal	high_lt:	   	std_logic;
+--signal	high_gt:		std_logic;
+--
+--signal	low_equals:		std_logic;
+--signal	low_lt:	   		std_logic;
+--signal	low_gt:			std_logic;
+--
+--signal	equals:			std_logic;
+--signal	less:			std_logic;
+--
+--begin
+--	u1: magnitude port map(
+--		a => a(3),
+--		b => b(3),
+--		equal => high_equals,
+--		lt => high_lt,
+--		gt => high_gt
+--	);
+--
+--	u2: magnitude3 port map(
+--		a => a(2 downto 0),
+--		b => b(2 downto 0),
+--		equal => low_equals,
+--		lt => low_lt,
+--		gt => low_gt
+--	);
+--
+--	equals <= high_equals and low_equals;
+--	less <= high_lt or (high_equals and low_lt);
+--	gt <= equals nor less;
+--	equal <= equals;
+--	lt <= less;
+--end;
+--
+--library	ieee;
+--use	ieee.std_logic_1164.all;
+--
+--entity magnitude5 is
+--port(
+--	a, b:	in	std_logic_vector(4 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end;
+--
+---- tested 2015/12/26 with modelsim, works.
+--
+--architecture struct_magnitude5 of magnitude5 is
+--component magnitude4 is
+--port(
+--	a, b:	in	std_logic_vector(3 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--component magnitude is
+--port(
+--	a, b:	in	std_logic;
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--signal	high_equals:	std_logic;
+--signal	high_lt:	   	std_logic;
+--signal	high_gt:		std_logic;
+--
+--signal	low_equals:		std_logic;
+--signal	low_lt:	   		std_logic;
+--signal	low_gt:			std_logic;
+--
+--signal	equals:			std_logic;
+--signal	less:			std_logic;
+--
+--begin
+--	u1: magnitude port map(
+--		a => a(4),
+--		b => b(4),
+--		equal => high_equals,
+--		lt => high_lt,
+--		gt => high_gt
+--	);
+--
+--	u2: magnitude4 port map(
+--		a => a(3 downto 0),
+--		b => b(3 downto 0),
+--		equal => low_equals,
+--		lt => low_lt,
+--		gt => low_gt
+--	);
+--
+--	equals <= high_equals and low_equals;
+--	less <= high_lt or (high_equals and low_lt);
+--	gt <= equals nor less;
+--	equal <= equals;
+--	lt <= less;
+--end;
+--
+--library	ieee;
+--use	ieee.std_logic_1164.all;
+--
+--entity magnitude6 is
+--port(
+--	a, b:	in	std_logic_vector(5 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end;
+--
+---- tested 2015/12/26 with modelsim, works.
+--
+--architecture struct_magnitude6 of magnitude6 is
+--component magnitude5 is
+--port(
+--	a, b:	in	std_logic_vector(4 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--component magnitude is
+--port(
+--	a, b:	in	std_logic;
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--signal	high_equals:	std_logic;
+--signal	high_lt:	   	std_logic;
+--signal	high_gt:		std_logic;
+--
+--signal	low_equals:		std_logic;
+--signal	low_lt:	   		std_logic;
+--signal	low_gt:			std_logic;
+--
+--signal	equals:			std_logic;
+--signal	less:			std_logic;
+--
+--begin
+--	u1: magnitude port map(
+--		a => a(5),
+--		b => b(5),
+--		equal => high_equals,
+--		lt => high_lt,
+--		gt => high_gt
+--	);
+--
+--	u2: magnitude5 port map(
+--		a => a(4 downto 0),
+--		b => b(4 downto 0),
+--		equal => low_equals,
+--		lt => low_lt,
+--		gt => low_gt
+--	);
+--
+--	equals <= high_equals and low_equals;
+--	less <= high_lt or (high_equals and low_lt);
+--	gt <= equals nor less;
+--	equal <= equals;
+--	lt <= less;
+--end;
+--
+--library	ieee;
+--use	ieee.std_logic_1164.all;
+--
+--entity magnitude7 is
+--port(
+--	a, b:	in	std_logic_vector(6 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end;
+--
+---- tested 2015/12/26 with modelsim, works.
+--
+--architecture struct_magnitude7 of magnitude7 is
+--component magnitude6 is
+--port(
+--	a, b:	in	std_logic_vector(5 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--component magnitude is
+--port(
+--	a, b:	in	std_logic;
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--signal	high_equals:	std_logic;
+--signal	high_lt:	   	std_logic;
+--signal	high_gt:		std_logic;
+--
+--signal	low_equals:		std_logic;
+--signal	low_lt:	   		std_logic;
+--signal	low_gt:			std_logic;
+--
+--signal	equals:			std_logic;
+--signal	less:			std_logic;
+--
+--begin
+--	u1: magnitude port map(
+--		a => a(6),
+--		b => b(6),
+--		equal => high_equals,
+--		lt => high_lt,
+--		gt => high_gt
+--	);
+--
+--	u2: magnitude6 port map(
+--		a => a(5 downto 0),
+--		b => b(5 downto 0),
+--		equal => low_equals,
+--		lt => low_lt,
+--		gt => low_gt
+--	);
+--
+--	equals <= high_equals and low_equals;
+--	less <= high_lt or (high_equals and low_lt);
+--	gt <= equals nor less;
+--	equal <= equals;
+--	lt <= less;
+--end;
+--
+--library	ieee;
+--use	ieee.std_logic_1164.all;
+--
+--entity magnitude8 is
+--port(
+--	a, b:	in	std_logic_vector(7 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end;
+--
+---- tested 2015/12/26 with modelsim, works.
+--architecture struct_magnitude8 of magnitude8 is
+--component magnitude7 is
+--port(
+--	a, b:	in	std_logic_vector(6 downto 0);
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--component magnitude is
+--port(
+--	a, b:	in	std_logic;
+--	equal:	out	std_logic;
+--	lt:		out	std_logic; 	-- '1' if a < b
+--	gt:		out	std_logic	-- '1' if a > b
+--);
+--end component;
+--
+--signal	high_equals:	std_logic;
+--signal	high_lt:	   	std_logic;
+--signal	high_gt:		std_logic;
+--
+--signal	low_equals:		std_logic;
+--signal	low_lt:	   		std_logic;
+--signal	low_gt:			std_logic;
+--
+--signal	equals:			std_logic;
+--signal	less:			std_logic;
+--
+--begin
+--	u1: magnitude port map(
+--		a => a(7),
+--		b => b(7),
+--		equal => high_equals,
+--		lt => high_lt,
+--		gt => high_gt
+--	);
+--
+--	u2: magnitude7 port map(
+--		a => a(6 downto 0),
+--		b => b(6 downto 0),
+--		equal => low_equals,
+--		lt => low_lt,
+--		gt => low_gt
+--	);
+--
+--	equals <= high_equals and low_equals;
+--	less <= high_lt or (high_equals and low_lt);
+--	gt <= equals nor less;
+--	equal <= equals;
+--	lt <= less;
+--end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity encoder64x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	data8:		in	std_logic;
+	data9:		in	std_logic;
+	data10:		in	std_logic;
+	data11:		in	std_logic;
+	data12:		in	std_logic;
+	data13:		in	std_logic;
+	data14:		in	std_logic;
+	data15:		in	std_logic;
+	data16:		in	std_logic;
+	data17:		in	std_logic;
+	data18:		in	std_logic;
+	data19:		in	std_logic;
+	data20:		in	std_logic;
+	data21:		in	std_logic;
+	data22:		in	std_logic;
+	data23:		in	std_logic;
+	data24:		in	std_logic;
+	data25:		in	std_logic;
+	data26:		in	std_logic;
+	data27:		in	std_logic;
+	data28:		in	std_logic;
+	data29:		in	std_logic;
+	data30:		in	std_logic;
+	data31:		in	std_logic;
+	data32:		in	std_logic;
+	data33:		in	std_logic;
+	data34:		in	std_logic;
+	data35:		in	std_logic;
+	data36:		in	std_logic;
+	data37:		in	std_logic;
+	data38:		in	std_logic;
+	data39:		in	std_logic;
+	data40:		in	std_logic;
+	data41:		in	std_logic;
+	data42:		in	std_logic;
+	data43:		in	std_logic;
+	data44:		in	std_logic;
+	data45:		in	std_logic;
+	data46:		in	std_logic;
+	data47:		in	std_logic;
+	data48:		in	std_logic;
+	data49:		in	std_logic;
+	data50:		in	std_logic;
+	data51:		in	std_logic;
+	data52:		in	std_logic;
+	data53:		in	std_logic;
+	data54:		in	std_logic;
+	data55:		in	std_logic;
+	data56:		in	std_logic;
+	data57:		in	std_logic;
+	data58:		in	std_logic;
+	data59:		in	std_logic;
+	data60:		in	std_logic;
+	data61:		in	std_logic;
+	data62:		in	std_logic;
+	data63:		in	std_logic;
+	address:	in	std_logic_vector(5 downto 0);
+	output:		out	std_logic
+);
+end;
+
+-- tested 2015/12/24 with modelsim as part of encoder64xN. works.
+
+architecture struct_encoder64x1 of encoder64x1 is
+begin
+	with address select
+		output <=
+			data0	when "000000",
+			data1	when "000001",
+			data2	when "000010",
+			data3	when "000011",
+			data4	when "000100",
+			data5	when "000101",
+			data6	when "000110",
+			data7	when "000111",
+			data8	when "001000",
+			data9	when "001001",
+			data10	when "001010",
+			data11	when "001011",
+			data12	when "001100",
+			data13	when "001101",
+			data14	when "001110",
+			data15	when "001111",
+			data16	when "010000",
+			data17	when "010001",
+			data18	when "010010",
+			data19	when "010011",
+			data20	when "010100",
+			data21	when "010101",
+			data22	when "010110",
+			data23	when "010111",
+			data24	when "011000",
+			data25	when "011001",
+			data26	when "011010",
+			data27	when "011011",
+			data28	when "011100",
+			data29	when "011101",
+			data30	when "011110",
+			data31	when "011111",
+			data32	when "100000",
+			data33	when "100001",
+			data34	when "100010",
+			data35	when "100011",
+			data36	when "100100",
+			data37	when "100101",
+			data38	when "100110",
+			data39	when "100111",
+			data40	when "101000",
+			data41	when "101001",
+			data42	when "101010",
+			data43	when "101011",
+			data44	when "101100",
+			data45	when "101101",
+			data46	when "101110",
+			data47	when "101111",
+			data48	when "110000",
+			data49	when "110001",
+			data50	when "110010",
+			data51	when "110011",
+			data52	when "110100",
+			data53	when "110101",
+			data54	when "110110",
+			data55	when "110111",
+			data56	when "111000",
+			data57	when "111001",
+			data58	when "111010",
+			data59	when "111011",
+			data60	when "111100",
+			data61	when "111101",
+			data62	when "111110",
+			data63	when "111111",
+			'0' when others;
+end;
+
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity encoder64xN is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	data2:		in	std_logic_vector((N-1) downto 0);
+	data3:		in	std_logic_vector((N-1) downto 0);
+	data4:		in	std_logic_vector((N-1) downto 0);
+	data5:		in	std_logic_vector((N-1) downto 0);
+	data6:		in	std_logic_vector((N-1) downto 0);
+	data7:		in	std_logic_vector((N-1) downto 0);
+	data8:		in	std_logic_vector((N-1) downto 0);
+	data9:		in	std_logic_vector((N-1) downto 0);
+	data10:		in	std_logic_vector((N-1) downto 0);
+	data11:		in	std_logic_vector((N-1) downto 0);
+	data12:		in	std_logic_vector((N-1) downto 0);
+	data13:		in	std_logic_vector((N-1) downto 0);
+	data14:		in	std_logic_vector((N-1) downto 0);
+	data15:		in	std_logic_vector((N-1) downto 0);
+	data16:		in	std_logic_vector((N-1) downto 0);
+	data17:		in	std_logic_vector((N-1) downto 0);
+	data18:		in	std_logic_vector((N-1) downto 0);
+	data19:		in	std_logic_vector((N-1) downto 0);
+	data20:		in	std_logic_vector((N-1) downto 0);
+	data21:		in	std_logic_vector((N-1) downto 0);
+	data22:		in	std_logic_vector((N-1) downto 0);
+	data23:		in	std_logic_vector((N-1) downto 0);
+	data24:		in	std_logic_vector((N-1) downto 0);
+	data25:		in	std_logic_vector((N-1) downto 0);
+	data26:		in	std_logic_vector((N-1) downto 0);
+	data27:		in	std_logic_vector((N-1) downto 0);
+	data28:		in	std_logic_vector((N-1) downto 0);
+	data29:		in	std_logic_vector((N-1) downto 0);
+	data30:		in	std_logic_vector((N-1) downto 0);
+	data31:		in	std_logic_vector((N-1) downto 0);
+	data32:		in	std_logic_vector((N-1) downto 0);
+	data33:		in	std_logic_vector((N-1) downto 0);
+	data34:		in	std_logic_vector((N-1) downto 0);
+	data35:		in	std_logic_vector((N-1) downto 0);
+	data36:		in	std_logic_vector((N-1) downto 0);
+	data37:		in	std_logic_vector((N-1) downto 0);
+	data38:		in	std_logic_vector((N-1) downto 0);
+	data39:		in	std_logic_vector((N-1) downto 0);
+	data40:		in	std_logic_vector((N-1) downto 0);
+	data41:		in	std_logic_vector((N-1) downto 0);
+	data42:		in	std_logic_vector((N-1) downto 0);
+	data43:		in	std_logic_vector((N-1) downto 0);
+	data44:		in	std_logic_vector((N-1) downto 0);
+	data45:		in	std_logic_vector((N-1) downto 0);
+	data46:		in	std_logic_vector((N-1) downto 0);
+	data47:		in	std_logic_vector((N-1) downto 0);
+	data48:		in	std_logic_vector((N-1) downto 0);
+	data49:		in	std_logic_vector((N-1) downto 0);
+	data50:		in	std_logic_vector((N-1) downto 0);
+	data51:		in	std_logic_vector((N-1) downto 0);
+	data52:		in	std_logic_vector((N-1) downto 0);
+	data53:		in	std_logic_vector((N-1) downto 0);
+	data54:		in	std_logic_vector((N-1) downto 0);
+	data55:		in	std_logic_vector((N-1) downto 0);
+	data56:		in	std_logic_vector((N-1) downto 0);
+	data57:		in	std_logic_vector((N-1) downto 0);
+	data58:		in	std_logic_vector((N-1) downto 0);
+	data59:		in	std_logic_vector((N-1) downto 0);
+	data60:		in	std_logic_vector((N-1) downto 0);
+	data61:		in	std_logic_vector((N-1) downto 0);
+	data62:		in	std_logic_vector((N-1) downto 0);
+	data63:		in	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(5 downto 0);
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+-- tested 2015/12/24 with modelsim and N = 8. works.
+
+architecture struct_encoder64xN of encoder64xN is
+component encoder64x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	data8:		in	std_logic;
+	data9:		in	std_logic;
+	data10:		in	std_logic;
+	data11:		in	std_logic;
+	data12:		in	std_logic;
+	data13:		in	std_logic;
+	data14:		in	std_logic;
+	data15:		in	std_logic;
+	data16:		in	std_logic;
+	data17:		in	std_logic;
+	data18:		in	std_logic;
+	data19:		in	std_logic;
+	data20:		in	std_logic;
+	data21:		in	std_logic;
+	data22:		in	std_logic;
+	data23:		in	std_logic;
+	data24:		in	std_logic;
+	data25:		in	std_logic;
+	data26:		in	std_logic;
+	data27:		in	std_logic;
+	data28:		in	std_logic;
+	data29:		in	std_logic;
+	data30:		in	std_logic;
+	data31:		in	std_logic;
+	data32:		in	std_logic;
+	data33:		in	std_logic;
+	data34:		in	std_logic;
+	data35:		in	std_logic;
+	data36:		in	std_logic;
+	data37:		in	std_logic;
+	data38:		in	std_logic;
+	data39:		in	std_logic;
+	data40:		in	std_logic;
+	data41:		in	std_logic;
+	data42:		in	std_logic;
+	data43:		in	std_logic;
+	data44:		in	std_logic;
+	data45:		in	std_logic;
+	data46:		in	std_logic;
+	data47:		in	std_logic;
+	data48:		in	std_logic;
+	data49:		in	std_logic;
+	data50:		in	std_logic;
+	data51:		in	std_logic;
+	data52:		in	std_logic;
+	data53:		in	std_logic;
+	data54:		in	std_logic;
+	data55:		in	std_logic;
+	data56:		in	std_logic;
+	data57:		in	std_logic;
+	data58:		in	std_logic;
+	data59:		in	std_logic;
+	data60:		in	std_logic;
+	data61:		in	std_logic;
+	data62:		in	std_logic;
+	data63:		in	std_logic;
+	address:	in	std_logic_vector(5 downto 0);
+	output:		out	std_logic
+);
+end component;
+
+begin
+	u1:	for i in 0 to (N-1) generate
+		u: encoder64x1 port map(
+			data0 => data0(i),
+			data1 => data1(i),
+			data2 => data2(i),
+			data3 => data3(i),
+			data4 => data4(i),
+			data5 => data5(i),
+			data6 => data6(i),
+			data7 => data7(i),
+			data8 => data8(i),
+			data9 => data9(i),
+			data10 => data10(i),
+			data11 => data11(i),
+			data12 => data12(i),
+			data13 => data13(i),
+			data14 => data14(i),
+			data15 => data15(i),
+			data16 => data16(i),
+			data17 => data17(i),
+			data18 => data18(i),
+			data19 => data19(i),
+			data20 => data20(i),
+			data21 => data21(i),
+			data22 => data22(i),
+			data23 => data23(i),
+			data24 => data24(i),
+			data25 => data25(i),
+			data26 => data26(i),
+			data27 => data27(i),
+			data28 => data28(i),
+			data29 => data29(i),
+			data30 => data30(i),
+			data31 => data31(i),
+			data32 => data32(i),
+			data33 => data33(i),
+			data34 => data34(i),
+			data35 => data35(i),
+			data36 => data36(i),
+			data37 => data37(i),
+			data38 => data38(i),
+			data39 => data39(i),
+			data40 => data40(i),
+			data41 => data41(i),
+			data42 => data42(i),
+			data43 => data43(i),
+			data44 => data44(i),
+			data45 => data45(i),
+			data46 => data46(i),
+			data47 => data47(i),
+			data48 => data48(i),
+			data49 => data49(i),
+			data50 => data50(i),
+			data51 => data51(i),
+			data52 => data52(i),
+			data53 => data53(i),
+			data54 => data54(i),
+			data55 => data55(i),
+			data56 => data56(i),
+			data57 => data57(i),
+			data58 => data58(i),
+			data59 => data59(i),
+			data60 => data60(i),
+			data61 => data61(i),
+			data62 => data62(i),
+			data63 => data63(i),
+			address => address,
+			output => output(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity decoder1x64 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	y16:		out	std_logic;
+	y17:		out	std_logic;
+	y18:		out	std_logic;
+	y19:		out	std_logic;
+	y20:		out	std_logic;
+	y21:		out	std_logic;
+	y22:		out	std_logic;
+	y23:		out	std_logic;
+	y24:		out	std_logic;
+	y25:		out	std_logic;
+	y26:		out	std_logic;
+	y27:		out	std_logic;
+	y28:		out	std_logic;
+	y29:		out	std_logic;
+	y30:		out	std_logic;
+	y31:		out	std_logic;
+	y32:		out	std_logic;
+	y33:		out	std_logic;
+	y34:		out	std_logic;
+	y35:		out	std_logic;
+	y36:		out	std_logic;
+	y37:		out	std_logic;
+	y38:		out	std_logic;
+	y39:		out	std_logic;
+	y40:		out	std_logic;
+	y41:		out	std_logic;
+	y42:		out	std_logic;
+	y43:		out	std_logic;
+	y44:		out	std_logic;
+	y45:		out	std_logic;
+	y46:		out	std_logic;
+	y47:		out	std_logic;
+	y48:		out	std_logic;
+	y49:		out	std_logic;
+	y50:		out	std_logic;
+	y51:		out	std_logic;
+	y52:		out	std_logic;
+	y53:		out	std_logic;
+	y54:		out	std_logic;
+	y55:		out	std_logic;
+	y56:		out	std_logic;
+	y57:		out	std_logic;
+	y58:		out	std_logic;
+	y59:		out	std_logic;
+	y60:		out	std_logic;
+	y61:		out	std_logic;
+	y62:		out	std_logic;
+	y63:		out	std_logic;
+	address:	in	std_logic_vector(5 downto 0)
+);
+end;
+
+-- tested 2015/12/26 as part of decoderNx64 using modelsim. works.
+
+architecture struct_decoder1x64 of decoder1x64 is
+begin
+	with address select y0 	<= data when "000000", '0' when others;
+	with address select y1	<= data when "000001", '0' when others;
+	with address select y2 	<= data when "000010", '0' when others;
+	with address select	y3	<= data when "000011", '0' when others;
+	with address select	y4	<= data when "000100", '0' when others;
+	with address select	y5	<= data when "000101", '0' when others;
+	with address select y6	<= data when "000110", '0' when others;
+	with address select y7	<= data when "000111", '0' when others;
+	with address select y8 	<= data when "001000", '0' when others;
+	with address select y9	<= data when "001001", '0' when others;
+	with address select y10	<= data when "001010", '0' when others;
+	with address select	y11	<= data when "001011", '0' when others;
+	with address select	y12	<= data when "001100", '0' when others;
+	with address select	y13	<= data when "001101", '0' when others;
+	with address select y14	<= data when "001110", '0' when others;
+	with address select y15	<= data when "001111", '0' when others;
+	with address select y16	<= data when "010000", '0' when others;
+	with address select y17	<= data when "010001", '0' when others;
+	with address select y18	<= data when "010010", '0' when others;
+	with address select	y19	<= data when "010011", '0' when others;
+	with address select	y20	<= data when "010100", '0' when others;
+	with address select	y21	<= data when "010101", '0' when others;
+	with address select y22	<= data when "010110", '0' when others;
+	with address select y23	<= data when "010111", '0' when others;
+	with address select y24	<= data when "011000", '0' when others;
+	with address select y25	<= data when "011001", '0' when others;
+	with address select y26	<= data when "011010", '0' when others;
+	with address select	y27	<= data when "011011", '0' when others;
+	with address select	y28	<= data when "011100", '0' when others;
+	with address select	y29	<= data when "011101", '0' when others;
+	with address select y30	<= data when "011110", '0' when others;
+	with address select y31	<= data when "011111", '0' when others;
+	with address select y32	<= data when "100000", '0' when others;
+	with address select y33	<= data when "100001", '0' when others;
+	with address select y34	<= data when "100010", '0' when others;
+	with address select	y35	<= data when "100011", '0' when others;
+	with address select	y36	<= data when "100100", '0' when others;
+	with address select	y37	<= data when "100101", '0' when others;
+	with address select y38	<= data when "100110", '0' when others;
+	with address select y39	<= data when "100111", '0' when others;
+	with address select y40	<= data when "101000", '0' when others;
+	with address select y41	<= data when "101001", '0' when others;
+	with address select y42	<= data when "101010", '0' when others;
+	with address select	y43	<= data when "101011", '0' when others;
+	with address select	y44	<= data when "101100", '0' when others;
+	with address select	y45	<= data when "101101", '0' when others;
+	with address select y46	<= data when "101110", '0' when others;
+	with address select y47	<= data when "101111", '0' when others;
+	with address select y48	<= data when "110000", '0' when others;
+	with address select y49	<= data when "110001", '0' when others;
+	with address select y50	<= data when "110010", '0' when others;
+	with address select	y51	<= data when "110011", '0' when others;
+	with address select	y52	<= data when "110100", '0' when others;
+	with address select	y53	<= data when "110101", '0' when others;
+	with address select y54	<= data when "110110", '0' when others;
+	with address select y55	<= data when "110111", '0' when others;
+	with address select y56	<= data when "111000", '0' when others;
+	with address select y57	<= data when "111001", '0' when others;
+	with address select y58	<= data when "111010", '0' when others;
+	with address select	y59	<= data when "111011", '0' when others;
+	with address select	y60	<= data when "111100", '0' when others;
+	with address select	y61	<= data when "111101", '0' when others;
+	with address select y62	<= data when "111110", '0' when others;
+	with address select y63	<= data when "111111", '0' when others;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity decoderNx64 is
+generic(
+	N:	positive
+);
+port(
+	data:		in	std_logic_vector((N-1) downto 0);
+	y0:			out	std_logic_vector((N-1) downto 0);
+	y1:			out	std_logic_vector((N-1) downto 0);
+	y2:			out	std_logic_vector((N-1) downto 0);
+	y3:			out	std_logic_vector((N-1) downto 0);
+	y4:			out	std_logic_vector((N-1) downto 0);
+	y5:			out	std_logic_vector((N-1) downto 0);
+	y6:			out	std_logic_vector((N-1) downto 0);
+	y7:			out	std_logic_vector((N-1) downto 0);
+	y8:			out	std_logic_vector((N-1) downto 0);
+	y9:			out	std_logic_vector((N-1) downto 0);
+	y10:		out	std_logic_vector((N-1) downto 0);
+	y11:		out	std_logic_vector((N-1) downto 0);
+	y12:		out	std_logic_vector((N-1) downto 0);
+	y13:		out	std_logic_vector((N-1) downto 0);
+	y14:		out	std_logic_vector((N-1) downto 0);
+	y15:		out	std_logic_vector((N-1) downto 0);
+	y16:		out	std_logic_vector((N-1) downto 0);
+	y17:		out	std_logic_vector((N-1) downto 0);
+	y18:		out	std_logic_vector((N-1) downto 0);
+	y19:		out	std_logic_vector((N-1) downto 0);
+	y20:		out	std_logic_vector((N-1) downto 0);
+	y21:		out	std_logic_vector((N-1) downto 0);
+	y22:		out	std_logic_vector((N-1) downto 0);
+	y23:		out	std_logic_vector((N-1) downto 0);
+	y24:		out	std_logic_vector((N-1) downto 0);
+	y25:		out	std_logic_vector((N-1) downto 0);
+	y26:		out	std_logic_vector((N-1) downto 0);
+	y27:		out	std_logic_vector((N-1) downto 0);
+	y28:		out	std_logic_vector((N-1) downto 0);
+	y29:		out	std_logic_vector((N-1) downto 0);
+	y30:		out	std_logic_vector((N-1) downto 0);
+	y31:		out	std_logic_vector((N-1) downto 0);
+	y32:		out	std_logic_vector((N-1) downto 0);
+	y33:		out	std_logic_vector((N-1) downto 0);
+	y34:		out	std_logic_vector((N-1) downto 0);
+	y35:		out	std_logic_vector((N-1) downto 0);
+	y36:		out	std_logic_vector((N-1) downto 0);
+	y37:		out	std_logic_vector((N-1) downto 0);
+	y38:		out	std_logic_vector((N-1) downto 0);
+	y39:		out	std_logic_vector((N-1) downto 0);
+	y40:		out	std_logic_vector((N-1) downto 0);
+	y41:		out	std_logic_vector((N-1) downto 0);
+	y42:		out	std_logic_vector((N-1) downto 0);
+	y43:		out	std_logic_vector((N-1) downto 0);
+	y44:		out	std_logic_vector((N-1) downto 0);
+	y45:		out	std_logic_vector((N-1) downto 0);
+	y46:		out	std_logic_vector((N-1) downto 0);
+	y47:		out	std_logic_vector((N-1) downto 0);
+	y48:		out	std_logic_vector((N-1) downto 0);
+	y49:		out	std_logic_vector((N-1) downto 0);
+	y50:		out	std_logic_vector((N-1) downto 0);
+	y51:		out	std_logic_vector((N-1) downto 0);
+	y52:		out	std_logic_vector((N-1) downto 0);
+	y53:		out	std_logic_vector((N-1) downto 0);
+	y54:		out	std_logic_vector((N-1) downto 0);
+	y55:		out	std_logic_vector((N-1) downto 0);
+	y56:		out	std_logic_vector((N-1) downto 0);
+	y57:		out	std_logic_vector((N-1) downto 0);
+	y58:		out	std_logic_vector((N-1) downto 0);
+	y59:		out	std_logic_vector((N-1) downto 0);
+	y60:		out	std_logic_vector((N-1) downto 0);
+	y61:		out	std_logic_vector((N-1) downto 0);
+	y62:		out	std_logic_vector((N-1) downto 0);
+	y63:		out	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(5 downto 0)
+);
+end;
+
+-- tested 2015/12/26 with N = 8 using modelsim. works.
+
+architecture struct_decoderNx64 of decoderNx64 is
+component decoder1x64 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	y16:		out	std_logic;
+	y17:		out	std_logic;
+	y18:		out	std_logic;
+	y19:		out	std_logic;
+	y20:		out	std_logic;
+	y21:		out	std_logic;
+	y22:		out	std_logic;
+	y23:		out	std_logic;
+	y24:		out	std_logic;
+	y25:		out	std_logic;
+	y26:		out	std_logic;
+	y27:		out	std_logic;
+	y28:		out	std_logic;
+	y29:		out	std_logic;
+	y30:		out	std_logic;
+	y31:		out	std_logic;
+	y32:		out	std_logic;
+	y33:		out	std_logic;
+	y34:		out	std_logic;
+	y35:		out	std_logic;
+	y36:		out	std_logic;
+	y37:		out	std_logic;
+	y38:		out	std_logic;
+	y39:		out	std_logic;
+	y40:		out	std_logic;
+	y41:		out	std_logic;
+	y42:		out	std_logic;
+	y43:		out	std_logic;
+	y44:		out	std_logic;
+	y45:		out	std_logic;
+	y46:		out	std_logic;
+	y47:		out	std_logic;
+	y48:		out	std_logic;
+	y49:		out	std_logic;
+	y50:		out	std_logic;
+	y51:		out	std_logic;
+	y52:		out	std_logic;
+	y53:		out	std_logic;
+	y54:		out	std_logic;
+	y55:		out	std_logic;
+	y56:		out	std_logic;
+	y57:		out	std_logic;
+	y58:		out	std_logic;
+	y59:		out	std_logic;
+	y60:		out	std_logic;
+	y61:		out	std_logic;
+	y62:		out	std_logic;
+	y63:		out	std_logic;
+	address:	in	std_logic_vector(5 downto 0)
+);
+end component;
+
+begin
+	u1:	for i in 0 to (N-1) generate
+		u: decoder1x64 port map(
+			data => data(i),
+			y0 => y0(i),
+			y1 => y1(i),
+			y2 => y2(i),
+			y3 => y3(i),
+			y4 => y4(i),
+			y5 => y5(i),
+			y6 => y6(i),
+			y7 => y7(i),
+			y8 => y8(i),
+			y9 => y9(i),
+			y10 => y10(i),
+			y11 => y11(i),
+			y12 => y12(i),
+			y13 => y13(i),
+			y14 => y14(i),
+			y15 => y15(i),
+			y16 => y16(i),
+			y17 => y17(i),
+			y18 => y18(i),
+			y19 => y19(i),
+			y20 => y20(i),
+			y21 => y21(i),
+			y22 => y22(i),
+			y23 => y23(i),
+			y24 => y24(i),
+			y25 => y25(i),
+			y26 => y26(i),
+			y27 => y27(i),
+			y28 => y28(i),
+			y29 => y29(i),
+			y30 => y30(i),
+			y31 => y31(i),
+			y32 => y32(i),
+			y33 => y33(i),
+			y34 => y34(i),
+			y35 => y35(i),
+			y36 => y36(i),
+			y37 => y37(i),
+			y38 => y38(i),
+			y39 => y39(i),
+			y40 => y40(i),
+			y41 => y41(i),
+			y42 => y42(i),
+			y43 => y43(i),
+			y44 => y44(i),
+			y45 => y45(i),
+			y46 => y46(i),
+			y47 => y47(i),
+			y48 => y48(i),
+			y49 => y49(i),
+			y50 => y50(i),
+			y51 => y51(i),
+			y52 => y52(i),
+			y53 => y53(i),
+			y54 => y54(i),
+			y55 => y55(i),
+			y56 => y56(i),
+			y57 => y57(i),
+			y58 => y58(i),
+			y59 => y59(i),
+			y60 => y60(i),
+			y61 => y61(i),
+			y62 => y62(i),
+			y63 => y63(i),
+			address => address
+		);
+	end generate;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity decoder1x32 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	y16:		out	std_logic;
+	y17:		out	std_logic;
+	y18:		out	std_logic;
+	y19:		out	std_logic;
+	y20:		out	std_logic;
+	y21:		out	std_logic;
+	y22:		out	std_logic;
+	y23:		out	std_logic;
+	y24:		out	std_logic;
+	y25:		out	std_logic;
+	y26:		out	std_logic;
+	y27:		out	std_logic;
+	y28:		out	std_logic;
+	y29:		out	std_logic;
+	y30:		out	std_logic;
+	y31:		out	std_logic;
+	address:	in	std_logic_vector(4 downto 0)
+);
+end;
+
+-- tested 2015/12/25 as part of decoderNx32 with modelsim, works.
+
+architecture struct_decoder1x32 of decoder1x32 is
+begin
+	with address select y0	<= data when "00000", '0' when others;
+	with address select y1	<= data when "00001", '0' when others;
+	with address select y2	<= data when "00010", '0' when others;
+	with address select y3	<= data when "00011", '0' when others;
+	with address select y4	<= data when "00100", '0' when others;
+	with address select y5	<= data when "00101", '0' when others;
+	with address select y6	<= data when "00110", '0' when others;
+	with address select y7	<= data when "00111", '0' when others;
+	with address select y8	<= data when "01000", '0' when others;
+	with address select y9	<= data when "01001", '0' when others;
+	with address select y10	<= data when "01010", '0' when others;
+	with address select y11	<= data when "01011", '0' when others;
+	with address select y12	<= data when "01100", '0' when others;
+	with address select y13	<= data when "01101", '0' when others;
+	with address select y14	<= data when "01110", '0' when others;
+	with address select y15	<= data when "01111", '0' when others;
+	with address select y16	<= data when "10000", '0' when others;
+	with address select y17	<= data when "10001", '0' when others;
+	with address select y18	<= data when "10010", '0' when others;
+	with address select y19	<= data when "10011", '0' when others;
+	with address select y20	<= data when "10100", '0' when others;
+	with address select y21	<= data when "10101", '0' when others;
+	with address select y22	<= data when "10110", '0' when others;
+	with address select y23	<= data when "10111", '0' when others;
+	with address select y24	<= data when "11000", '0' when others;
+	with address select y25	<= data when "11001", '0' when others;
+	with address select y26	<= data when "11010", '0' when others;
+	with address select y27	<= data when "11011", '0' when others;
+	with address select y28	<= data when "11100", '0' when others;
+	with address select y29	<= data when "11101", '0' when others;
+	with address select y30	<= data when "11110", '0' when others;
+	with address select y31	<= data when "11111", '0' when others;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity decoderNx32 is
+generic(
+	N:	positive
+);
+port(
+	data:		in	std_logic_vector((N-1) downto 0);
+	y0:			out	std_logic_vector((N-1) downto 0);
+	y1:			out	std_logic_vector((N-1) downto 0);
+	y2:			out	std_logic_vector((N-1) downto 0);
+	y3:			out	std_logic_vector((N-1) downto 0);
+	y4:			out	std_logic_vector((N-1) downto 0);
+	y5:			out	std_logic_vector((N-1) downto 0);
+	y6:			out	std_logic_vector((N-1) downto 0);
+	y7:			out	std_logic_vector((N-1) downto 0);
+	y8:			out	std_logic_vector((N-1) downto 0);
+	y9:			out	std_logic_vector((N-1) downto 0);
+	y10:		out	std_logic_vector((N-1) downto 0);
+	y11:		out	std_logic_vector((N-1) downto 0);
+	y12:		out	std_logic_vector((N-1) downto 0);
+	y13:		out	std_logic_vector((N-1) downto 0);
+	y14:		out	std_logic_vector((N-1) downto 0);
+	y15:		out	std_logic_vector((N-1) downto 0);
+	y16:		out	std_logic_vector((N-1) downto 0);
+	y17:		out	std_logic_vector((N-1) downto 0);
+	y18:		out	std_logic_vector((N-1) downto 0);
+	y19:		out	std_logic_vector((N-1) downto 0);
+	y20:		out	std_logic_vector((N-1) downto 0);
+	y21:		out	std_logic_vector((N-1) downto 0);
+	y22:		out	std_logic_vector((N-1) downto 0);
+	y23:		out	std_logic_vector((N-1) downto 0);
+	y24:		out	std_logic_vector((N-1) downto 0);
+	y25:		out	std_logic_vector((N-1) downto 0);
+	y26:		out	std_logic_vector((N-1) downto 0);
+	y27:		out	std_logic_vector((N-1) downto 0);
+	y28:		out	std_logic_vector((N-1) downto 0);
+	y29:		out	std_logic_vector((N-1) downto 0);
+	y30:		out	std_logic_vector((N-1) downto 0);
+	y31:		out	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(4 downto 0)
+);
+end;
+
+-- tested 2015/12/25 with modelsim and N = 8, works.
+-- reverified with correct report statements 2015/12/26,  works.
+
+architecture struct_decoderNx32 of decoderNx32 is
+component decoder1x32 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	y16:		out	std_logic;
+	y17:		out	std_logic;
+	y18:		out	std_logic;
+	y19:		out	std_logic;
+	y20:		out	std_logic;
+	y21:		out	std_logic;
+	y22:		out	std_logic;
+	y23:		out	std_logic;
+	y24:		out	std_logic;
+	y25:		out	std_logic;
+	y26:		out	std_logic;
+	y27:		out	std_logic;
+	y28:		out	std_logic;
+	y29:		out	std_logic;
+	y30:		out	std_logic;
+	y31:		out	std_logic;
+	address:	in	std_logic_vector(4 downto 0)
+);
+end component;
+
+begin
+	u1:	for i in 0 to (N-1) generate
+		u: decoder1x32 port map(
+			data => data(i),
+			y0 => y0(i),
+			y1 => y1(i),
+			y2 => y2(i),
+			y3 => y3(i),
+			y4 => y4(i),
+			y5 => y5(i),
+			y6 => y6(i),
+			y7 => y7(i),
+			y8 => y8(i),
+			y9 => y9(i),
+			y10	=> y10(i),
+			y11	=> y11(i),
+			y12	=> y12(i),
+			y13	=> y13(i),
+			y14	=> y14(i),
+			y15	=> y15(i),
+			y16	=> y16(i),
+			y17	=> y17(i),
+			y18	=> y18(i),
+			y19	=> y19(i),
+			y20	=> y20(i),
+			y21	=> y21(i),
+			y22	=> y22(i),
+			y23	=> y23(i),
+			y24	=> y24(i),
+			y25	=> y25(i),
+			y26	=> y26(i),
+			y27	=> y27(i),
+			y28	=> y28(i),
+			y29	=> y29(i),
+			y30	=> y30(i),
+			y31	=> y31(i),
+			address => address
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity encoder128x1 is
+port(
+	data0:			in	std_logic;
+	data1:			in	std_logic;
+	data2:			in	std_logic;
+	data3:			in	std_logic;
+	data4:			in	std_logic;
+	data5:			in	std_logic;
+	data6:			in	std_logic;
+	data7:			in	std_logic;
+	data8:			in	std_logic;
+	data9:			in	std_logic;
+	data10:			in	std_logic;
+	data11:			in	std_logic;
+	data12:			in	std_logic;
+	data13:			in	std_logic;
+	data14:			in	std_logic;
+	data15:			in	std_logic;
+	data16:			in	std_logic;
+	data17:			in	std_logic;
+	data18:			in	std_logic;
+	data19:			in	std_logic;
+	data20:			in	std_logic;
+	data21:			in	std_logic;
+	data22:			in	std_logic;
+	data23:			in	std_logic;
+	data24:			in	std_logic;
+	data25:			in	std_logic;
+	data26:			in	std_logic;
+	data27:			in	std_logic;
+	data28:			in	std_logic;
+	data29:			in	std_logic;
+	data30:			in	std_logic;
+	data31:			in	std_logic;
+	data32:			in	std_logic;
+	data33:			in	std_logic;
+	data34:			in	std_logic;
+	data35:			in	std_logic;
+	data36:			in	std_logic;
+	data37:			in	std_logic;
+	data38:			in	std_logic;
+	data39:			in	std_logic;
+	data40:			in	std_logic;
+	data41:			in	std_logic;
+	data42:			in	std_logic;
+	data43:			in	std_logic;
+	data44:			in	std_logic;
+	data45:			in	std_logic;
+	data46:			in	std_logic;
+	data47:			in	std_logic;
+	data48:			in	std_logic;
+	data49:			in	std_logic;
+	data50:			in	std_logic;
+	data51:			in	std_logic;
+	data52:			in	std_logic;
+	data53:			in	std_logic;
+	data54:			in	std_logic;
+	data55:			in	std_logic;
+	data56:			in	std_logic;
+	data57:			in	std_logic;
+	data58:			in	std_logic;
+	data59:			in	std_logic;
+	data60:			in	std_logic;
+	data61:			in	std_logic;
+	data62:			in	std_logic;
+	data63:			in	std_logic;
+	data64:			in	std_logic;
+	data65:			in	std_logic;
+	data66:			in	std_logic;
+	data67:			in	std_logic;
+	data68:			in	std_logic;
+	data69:			in	std_logic;
+	data70:			in	std_logic;
+	data71:			in	std_logic;
+	data72:			in	std_logic;
+	data73:			in	std_logic;
+	data74:			in	std_logic;
+	data75:			in	std_logic;
+	data76:			in	std_logic;
+	data77:			in	std_logic;
+	data78:			in	std_logic;
+	data79:			in	std_logic;
+	data80:			in	std_logic;
+	data81:			in	std_logic;
+	data82:			in	std_logic;
+	data83:			in	std_logic;
+	data84:			in	std_logic;
+	data85:			in	std_logic;
+	data86:			in	std_logic;
+	data87:			in	std_logic;
+	data88:			in	std_logic;
+	data89:			in	std_logic;
+	data90:			in	std_logic;
+	data91:			in	std_logic;
+	data92:			in	std_logic;
+	data93:			in	std_logic;
+	data94:			in	std_logic;
+	data95:			in	std_logic;
+	data96:			in	std_logic;
+	data97:			in	std_logic;
+	data98:			in	std_logic;
+	data99:			in	std_logic;
+	data100:		in	std_logic;
+	data101:		in	std_logic;
+	data102:		in	std_logic;
+	data103:		in	std_logic;
+	data104:		in	std_logic;
+	data105:		in	std_logic;
+	data106:		in	std_logic;
+	data107:		in	std_logic;
+	data108:		in	std_logic;
+	data109:		in	std_logic;
+	data110:		in	std_logic;
+	data111:		in	std_logic;
+	data112:		in	std_logic;
+	data113:		in	std_logic;
+	data114:		in	std_logic;
+	data115:		in	std_logic;
+	data116:		in	std_logic;
+	data117:		in	std_logic;
+	data118:		in	std_logic;
+	data119:		in	std_logic;
+	data120:		in	std_logic;
+	data121:		in	std_logic;
+	data122:		in	std_logic;
+	data123:		in	std_logic;
+	data124:		in	std_logic;
+	data125:		in	std_logic;
+	data126:		in	std_logic;
+	data127:		in	std_logic;
+	address:		in	std_logic_vector(6 downto 0);
+	output:			out	std_logic
+);
+end;
+
+architecture struct_encoder128x1 of encoder128x1 is
+begin
+	with address select
+		output <=
+			data0	when "0000000",
+			data1	when "0000001",
+			data2	when "0000010",
+			data3	when "0000011",
+			data4	when "0000100",
+			data5	when "0000101",
+			data6	when "0000110",
+			data7	when "0000111",
+			data8	when "0001000",
+			data9	when "0001001",
+			data10	when "0001010",
+			data11	when "0001011",
+			data12	when "0001100",
+			data13	when "0001101",
+			data14	when "0001110",
+			data15	when "0001111",
+			data16	when "0010000",
+			data17	when "0010001",
+			data18	when "0010010",
+			data19	when "0010011",
+			data20	when "0010100",
+			data21	when "0010101",
+			data22	when "0010110",
+			data23	when "0010111",
+			data24	when "0011000",
+			data25	when "0011001",
+			data26	when "0011010",
+			data27	when "0011011",
+			data28	when "0011100",
+			data29	when "0011101",
+			data30	when "0011110",
+			data31	when "0011111",
+			data32	when "0100000",
+			data33	when "0100001",
+			data34	when "0100010",
+			data35	when "0100011",
+			data36	when "0100100",
+			data37	when "0100101",
+			data38	when "0100110",
+			data39	when "0100111",
+			data40	when "0101000",
+			data41	when "0101001",
+			data42	when "0101010",
+			data43	when "0101011",
+			data44	when "0101100",
+			data45	when "0101101",
+			data46	when "0101110",
+			data47	when "0101111",
+			data48	when "0110000",
+			data49	when "0110001",
+			data50	when "0110010",
+			data51	when "0110011",
+			data52	when "0110100",
+			data53	when "0110101",
+			data54	when "0110110",
+			data55	when "0110111",
+			data56	when "0111000",
+			data57	when "0111001",
+			data58	when "0111010",
+			data59	when "0111011",
+			data60	when "0111100",
+			data61	when "0111101",
+			data62	when "0111110",
+			data63	when "0111111",
+			data64	when "1000000",
+			data65	when "1000001",
+			data66	when "1000010",
+			data67	when "1000011",
+			data68	when "1000100",
+			data69	when "1000101",
+			data70	when "1000110",
+			data71	when "1000111",
+			data72	when "1001000",
+			data73	when "1001001",
+			data74	when "1001010",
+			data75	when "1001011",
+			data76	when "1001100",
+			data77	when "1001101",
+			data78	when "1001110",
+			data79	when "1001111",
+			data80	when "1010000",
+			data81	when "1010001",
+			data82	when "1010010",
+			data83	when "1010011",
+			data84	when "1010100",
+			data85	when "1010101",
+			data86	when "1010110",
+			data87	when "1010111",
+			data88	when "1011000",
+			data89	when "1011001",
+			data90	when "1011010",
+			data91	when "1011011",
+			data92	when "1011100",
+			data93	when "1011101",
+			data94	when "1011110",
+			data95	when "1011111",
+			data96	when "1100000",
+			data97	when "1100001",
+			data98	when "1100010",
+			data99	when "1100011",
+			data100	when "1100100",
+			data101	when "1100101",
+			data102	when "1100110",
+			data103	when "1100111",
+			data104	when "1101000",
+			data105	when "1101001",
+			data106	when "1101010",
+			data107	when "1101011",
+			data108	when "1101100",
+			data109	when "1101101",
+			data110	when "1101110",
+			data111	when "1101111",
+			data112	when "1110000",
+			data113	when "1110001",
+			data114	when "1110010",
+			data115	when "1110011",
+			data116	when "1110100",
+			data117	when "1110101",
+			data118	when "1110110",
+			data119	when "1110111",
+			data120	when "1111000",
+			data121	when "1111001",
+			data122	when "1111010",
+			data123	when "1111011",
+			data124	when "1111100",
+			data125	when "1111101",
+			data126	when "1111110",
+			data127	when "1111111",
+			'0' when others;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity encoder128xN is
+generic(
+	N: positive
+);
+port(
+	data0:			in	std_logic_vector((N-1) downto 0);
+	data1:			in	std_logic_vector((N-1) downto 0);
+	data2:			in	std_logic_vector((N-1) downto 0);
+	data3:			in	std_logic_vector((N-1) downto 0);
+	data4:			in	std_logic_vector((N-1) downto 0);
+	data5:			in	std_logic_vector((N-1) downto 0);
+	data6:			in	std_logic_vector((N-1) downto 0);
+	data7:			in	std_logic_vector((N-1) downto 0);
+	data8:			in	std_logic_vector((N-1) downto 0);
+	data9:			in	std_logic_vector((N-1) downto 0);
+	data10:			in	std_logic_vector((N-1) downto 0);
+	data11:			in	std_logic_vector((N-1) downto 0);
+	data12:			in	std_logic_vector((N-1) downto 0);
+	data13:			in	std_logic_vector((N-1) downto 0);
+	data14:			in	std_logic_vector((N-1) downto 0);
+	data15:			in	std_logic_vector((N-1) downto 0);
+	data16:			in	std_logic_vector((N-1) downto 0);
+	data17:			in	std_logic_vector((N-1) downto 0);
+	data18:			in	std_logic_vector((N-1) downto 0);
+	data19:			in	std_logic_vector((N-1) downto 0);
+	data20:			in	std_logic_vector((N-1) downto 0);
+	data21:			in	std_logic_vector((N-1) downto 0);
+	data22:			in	std_logic_vector((N-1) downto 0);
+	data23:			in	std_logic_vector((N-1) downto 0);
+	data24:			in	std_logic_vector((N-1) downto 0);
+	data25:			in	std_logic_vector((N-1) downto 0);
+	data26:			in	std_logic_vector((N-1) downto 0);
+	data27:			in	std_logic_vector((N-1) downto 0);
+	data28:			in	std_logic_vector((N-1) downto 0);
+	data29:			in	std_logic_vector((N-1) downto 0);
+	data30:			in	std_logic_vector((N-1) downto 0);
+	data31:			in	std_logic_vector((N-1) downto 0);
+	data32:			in	std_logic_vector((N-1) downto 0);
+	data33:			in	std_logic_vector((N-1) downto 0);
+	data34:			in	std_logic_vector((N-1) downto 0);
+	data35:			in	std_logic_vector((N-1) downto 0);
+	data36:			in	std_logic_vector((N-1) downto 0);
+	data37:			in	std_logic_vector((N-1) downto 0);
+	data38:			in	std_logic_vector((N-1) downto 0);
+	data39:			in	std_logic_vector((N-1) downto 0);
+	data40:			in	std_logic_vector((N-1) downto 0);
+	data41:			in	std_logic_vector((N-1) downto 0);
+	data42:			in	std_logic_vector((N-1) downto 0);
+	data43:			in	std_logic_vector((N-1) downto 0);
+	data44:			in	std_logic_vector((N-1) downto 0);
+	data45:			in	std_logic_vector((N-1) downto 0);
+	data46:			in	std_logic_vector((N-1) downto 0);
+	data47:			in	std_logic_vector((N-1) downto 0);
+	data48:			in	std_logic_vector((N-1) downto 0);
+	data49:			in	std_logic_vector((N-1) downto 0);
+	data50:			in	std_logic_vector((N-1) downto 0);
+	data51:			in	std_logic_vector((N-1) downto 0);
+	data52:			in	std_logic_vector((N-1) downto 0);
+	data53:			in	std_logic_vector((N-1) downto 0);
+	data54:			in	std_logic_vector((N-1) downto 0);
+	data55:			in	std_logic_vector((N-1) downto 0);
+	data56:			in	std_logic_vector((N-1) downto 0);
+	data57:			in	std_logic_vector((N-1) downto 0);
+	data58:			in	std_logic_vector((N-1) downto 0);
+	data59:			in	std_logic_vector((N-1) downto 0);
+	data60:			in	std_logic_vector((N-1) downto 0);
+	data61:			in	std_logic_vector((N-1) downto 0);
+	data62:			in	std_logic_vector((N-1) downto 0);
+	data63:			in	std_logic_vector((N-1) downto 0);
+	data64:			in	std_logic_vector((N-1) downto 0);
+	data65:			in	std_logic_vector((N-1) downto 0);
+	data66:			in	std_logic_vector((N-1) downto 0);
+	data67:			in	std_logic_vector((N-1) downto 0);
+	data68:			in	std_logic_vector((N-1) downto 0);
+	data69:			in	std_logic_vector((N-1) downto 0);
+	data70:			in	std_logic_vector((N-1) downto 0);
+	data71:			in	std_logic_vector((N-1) downto 0);
+	data72:			in	std_logic_vector((N-1) downto 0);
+	data73:			in	std_logic_vector((N-1) downto 0);
+	data74:			in	std_logic_vector((N-1) downto 0);
+	data75:			in	std_logic_vector((N-1) downto 0);
+	data76:			in	std_logic_vector((N-1) downto 0);
+	data77:			in	std_logic_vector((N-1) downto 0);
+	data78:			in	std_logic_vector((N-1) downto 0);
+	data79:			in	std_logic_vector((N-1) downto 0);
+	data80:			in	std_logic_vector((N-1) downto 0);
+	data81:			in	std_logic_vector((N-1) downto 0);
+	data82:			in	std_logic_vector((N-1) downto 0);
+	data83:			in	std_logic_vector((N-1) downto 0);
+	data84:			in	std_logic_vector((N-1) downto 0);
+	data85:			in	std_logic_vector((N-1) downto 0);
+	data86:			in	std_logic_vector((N-1) downto 0);
+	data87:			in	std_logic_vector((N-1) downto 0);
+	data88:			in	std_logic_vector((N-1) downto 0);
+	data89:			in	std_logic_vector((N-1) downto 0);
+	data90:			in	std_logic_vector((N-1) downto 0);
+	data91:			in	std_logic_vector((N-1) downto 0);
+	data92:			in	std_logic_vector((N-1) downto 0);
+	data93:			in	std_logic_vector((N-1) downto 0);
+	data94:			in	std_logic_vector((N-1) downto 0);
+	data95:			in	std_logic_vector((N-1) downto 0);
+	data96:			in	std_logic_vector((N-1) downto 0);
+	data97:			in	std_logic_vector((N-1) downto 0);
+	data98:			in	std_logic_vector((N-1) downto 0);
+	data99:			in	std_logic_vector((N-1) downto 0);
+	data100:		in	std_logic_vector((N-1) downto 0);
+	data101:		in	std_logic_vector((N-1) downto 0);
+	data102:		in	std_logic_vector((N-1) downto 0);
+	data103:		in	std_logic_vector((N-1) downto 0);
+	data104:		in	std_logic_vector((N-1) downto 0);
+	data105:		in	std_logic_vector((N-1) downto 0);
+	data106:		in	std_logic_vector((N-1) downto 0);
+	data107:		in	std_logic_vector((N-1) downto 0);
+	data108:		in	std_logic_vector((N-1) downto 0);
+	data109:		in	std_logic_vector((N-1) downto 0);
+	data110:		in	std_logic_vector((N-1) downto 0);
+	data111:		in	std_logic_vector((N-1) downto 0);
+	data112:		in	std_logic_vector((N-1) downto 0);
+	data113:		in	std_logic_vector((N-1) downto 0);
+	data114:		in	std_logic_vector((N-1) downto 0);
+	data115:		in	std_logic_vector((N-1) downto 0);
+	data116:		in	std_logic_vector((N-1) downto 0);
+	data117:		in	std_logic_vector((N-1) downto 0);
+	data118:		in	std_logic_vector((N-1) downto 0);
+	data119:		in	std_logic_vector((N-1) downto 0);
+	data120:		in	std_logic_vector((N-1) downto 0);
+	data121:		in	std_logic_vector((N-1) downto 0);
+	data122:		in	std_logic_vector((N-1) downto 0);
+	data123:		in	std_logic_vector((N-1) downto 0);
+	data124:		in	std_logic_vector((N-1) downto 0);
+	data125:		in	std_logic_vector((N-1) downto 0);
+	data126:		in	std_logic_vector((N-1) downto 0);
+	data127:		in	std_logic_vector((N-1) downto 0);
+	address:		in	std_logic_vector(6 downto 0);
+	output:			out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+architecture struct_encoder128xN of encoder128xN is
+component encoder128x1 is
+port(
+	data0:			in	std_logic;
+	data1:			in	std_logic;
+	data2:			in	std_logic;
+	data3:			in	std_logic;
+	data4:			in	std_logic;
+	data5:			in	std_logic;
+	data6:			in	std_logic;
+	data7:			in	std_logic;
+	data8:			in	std_logic;
+	data9:			in	std_logic;
+	data10:			in	std_logic;
+	data11:			in	std_logic;
+	data12:			in	std_logic;
+	data13:			in	std_logic;
+	data14:			in	std_logic;
+	data15:			in	std_logic;
+	data16:			in	std_logic;
+	data17:			in	std_logic;
+	data18:			in	std_logic;
+	data19:			in	std_logic;
+	data20:			in	std_logic;
+	data21:			in	std_logic;
+	data22:			in	std_logic;
+	data23:			in	std_logic;
+	data24:			in	std_logic;
+	data25:			in	std_logic;
+	data26:			in	std_logic;
+	data27:			in	std_logic;
+	data28:			in	std_logic;
+	data29:			in	std_logic;
+	data30:			in	std_logic;
+	data31:			in	std_logic;
+	data32:			in	std_logic;
+	data33:			in	std_logic;
+	data34:			in	std_logic;
+	data35:			in	std_logic;
+	data36:			in	std_logic;
+	data37:			in	std_logic;
+	data38:			in	std_logic;
+	data39:			in	std_logic;
+	data40:			in	std_logic;
+	data41:			in	std_logic;
+	data42:			in	std_logic;
+	data43:			in	std_logic;
+	data44:			in	std_logic;
+	data45:			in	std_logic;
+	data46:			in	std_logic;
+	data47:			in	std_logic;
+	data48:			in	std_logic;
+	data49:			in	std_logic;
+	data50:			in	std_logic;
+	data51:			in	std_logic;
+	data52:			in	std_logic;
+	data53:			in	std_logic;
+	data54:			in	std_logic;
+	data55:			in	std_logic;
+	data56:			in	std_logic;
+	data57:			in	std_logic;
+	data58:			in	std_logic;
+	data59:			in	std_logic;
+	data60:			in	std_logic;
+	data61:			in	std_logic;
+	data62:			in	std_logic;
+	data63:			in	std_logic;
+	data64:			in	std_logic;
+	data65:			in	std_logic;
+	data66:			in	std_logic;
+	data67:			in	std_logic;
+	data68:			in	std_logic;
+	data69:			in	std_logic;
+	data70:			in	std_logic;
+	data71:			in	std_logic;
+	data72:			in	std_logic;
+	data73:			in	std_logic;
+	data74:			in	std_logic;
+	data75:			in	std_logic;
+	data76:			in	std_logic;
+	data77:			in	std_logic;
+	data78:			in	std_logic;
+	data79:			in	std_logic;
+	data80:			in	std_logic;
+	data81:			in	std_logic;
+	data82:			in	std_logic;
+	data83:			in	std_logic;
+	data84:			in	std_logic;
+	data85:			in	std_logic;
+	data86:			in	std_logic;
+	data87:			in	std_logic;
+	data88:			in	std_logic;
+	data89:			in	std_logic;
+	data90:			in	std_logic;
+	data91:			in	std_logic;
+	data92:			in	std_logic;
+	data93:			in	std_logic;
+	data94:			in	std_logic;
+	data95:			in	std_logic;
+	data96:			in	std_logic;
+	data97:			in	std_logic;
+	data98:			in	std_logic;
+	data99:			in	std_logic;
+	data100:		in	std_logic;
+	data101:		in	std_logic;
+	data102:		in	std_logic;
+	data103:		in	std_logic;
+	data104:		in	std_logic;
+	data105:		in	std_logic;
+	data106:		in	std_logic;
+	data107:		in	std_logic;
+	data108:		in	std_logic;
+	data109:		in	std_logic;
+	data110:		in	std_logic;
+	data111:		in	std_logic;
+	data112:		in	std_logic;
+	data113:		in	std_logic;
+	data114:		in	std_logic;
+	data115:		in	std_logic;
+	data116:		in	std_logic;
+	data117:		in	std_logic;
+	data118:		in	std_logic;
+	data119:		in	std_logic;
+	data120:		in	std_logic;
+	data121:		in	std_logic;
+	data122:		in	std_logic;
+	data123:		in	std_logic;
+	data124:		in	std_logic;
+	data125:		in	std_logic;
+	data126:		in	std_logic;
+	data127:		in	std_logic;
+	address:		in	std_logic_vector(6 downto 0);
+	output:			out	std_logic
+);
+end component;
+
+begin
+	u1:	for i in (N-1) downto 0 generate
+		u: encoder128x1 port map(
+			data0	=> data0(i),
+			data1	=> data1(i),
+			data2	=> data2(i),
+			data3	=> data3(i),
+			data4	=> data4(i),
+			data5	=> data5(i),
+			data6	=> data6(i),
+			data7	=> data7(i),
+			data8	=> data8(i),
+			data9	=> data9(i),
+			data10	=> data10(i),
+			data11	=> data11(i),
+			data12	=> data12(i),
+			data13	=> data13(i),
+			data14	=> data14(i),
+			data15	=> data15(i),
+			data16	=> data16(i),
+			data17	=> data17(i),
+			data18	=> data18(i),
+			data19	=> data19(i),
+			data20	=> data20(i),
+			data21	=> data21(i),
+			data22	=> data22(i),
+			data23	=> data23(i),
+			data24	=> data24(i),
+			data25	=> data25(i),
+			data26	=> data26(i),
+			data27	=> data27(i),
+			data28	=> data28(i),
+			data29	=> data29(i),
+			data30	=> data30(i),
+			data31	=> data31(i),
+			data32	=> data32(i),
+			data33	=> data33(i),
+			data34	=> data34(i),
+			data35	=> data35(i),
+			data36	=> data36(i),
+			data37	=> data37(i),
+			data38	=> data38(i),
+			data39	=> data39(i),
+			data40	=> data40(i),
+			data41	=> data41(i),
+			data42	=> data42(i),
+			data43	=> data43(i),
+			data44	=> data44(i),
+			data45	=> data45(i),
+			data46	=> data46(i),
+			data47	=> data47(i),
+			data48	=> data48(i),
+			data49	=> data49(i),
+			data50	=> data50(i),
+			data51	=> data51(i),
+			data52	=> data52(i),
+			data53	=> data53(i),
+			data54	=> data54(i),
+			data55	=> data55(i),
+			data56	=> data56(i),
+			data57	=> data57(i),
+			data58	=> data58(i),
+			data59	=> data59(i),
+			data60	=> data60(i),
+			data61	=> data61(i),
+			data62	=> data62(i),
+			data63	=> data63(i),
+			data64	=> data64(i),
+			data65	=> data65(i),
+			data66	=> data66(i),
+			data67	=> data67(i),
+			data68	=> data68(i),
+			data69	=> data69(i),
+			data70	=> data70(i),
+			data71	=> data71(i),
+			data72	=> data72(i),
+			data73	=> data73(i),
+			data74	=> data74(i),
+			data75	=> data75(i),
+			data76	=> data76(i),
+			data77	=> data77(i),
+			data78	=> data78(i),
+			data79	=> data79(i),
+			data80	=> data80(i),
+			data81	=> data81(i),
+			data82	=> data82(i),
+			data83	=> data83(i),
+			data84	=> data84(i),
+			data85	=> data85(i),
+			data86	=> data86(i),
+			data87	=> data87(i),
+			data88	=> data88(i),
+			data89	=> data89(i),
+			data90	=> data90(i),
+			data91	=> data91(i),
+			data92	=> data92(i),
+			data93	=> data93(i),
+			data94	=> data94(i),
+			data95	=> data95(i),
+			data96	=> data96(i),
+			data97	=> data97(i),
+			data98	=> data98(i),
+			data99	=> data99(i),
+			data100	=> data100(i),
+			data101	=> data101(i),
+			data102	=> data102(i),
+			data103	=> data103(i),
+			data104	=> data104(i),
+			data105	=> data105(i),
+			data106	=> data106(i),
+			data107	=> data107(i),
+			data108	=> data108(i),
+			data109	=> data109(i),
+			data110	=> data110(i),
+			data111	=> data111(i),
+			data112	=> data112(i),
+			data113	=> data113(i),
+			data114	=> data114(i),
+			data115	=> data115(i),
+			data116	=> data116(i),
+			data117	=> data117(i),
+			data118	=> data118(i),
+			data119	=> data119(i),
+			data120	=> data120(i),
+			data121	=> data121(i),
+			data122	=> data122(i),
+			data123	=> data123(i),
+			data124	=> data124(i),
+			data125	=> data125(i),
+			data126	=> data126(i),
+			data127	=> data127(i),
+			address	=> address,
+			output => output(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity decoder1x128 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	y16:		out	std_logic;
+	y17:		out	std_logic;
+	y18:		out	std_logic;
+	y19:		out	std_logic;
+	y20:		out	std_logic;
+	y21:		out	std_logic;
+	y22:		out	std_logic;
+	y23:		out	std_logic;
+	y24:		out	std_logic;
+	y25:		out	std_logic;
+	y26:		out	std_logic;
+	y27:		out	std_logic;
+	y28:		out	std_logic;
+	y29:		out	std_logic;
+	y30:		out	std_logic;
+	y31:		out	std_logic;
+	y32:		out	std_logic;
+	y33:		out	std_logic;
+	y34:		out	std_logic;
+	y35:		out	std_logic;
+	y36:		out	std_logic;
+	y37:		out	std_logic;
+	y38:		out	std_logic;
+	y39:		out	std_logic;
+	y40:		out	std_logic;
+	y41:		out	std_logic;
+	y42:		out	std_logic;
+	y43:		out	std_logic;
+	y44:		out	std_logic;
+	y45:		out	std_logic;
+	y46:		out	std_logic;
+	y47:		out	std_logic;
+	y48:		out	std_logic;
+	y49:		out	std_logic;
+	y50:		out	std_logic;
+	y51:		out	std_logic;
+	y52:		out	std_logic;
+	y53:		out	std_logic;
+	y54:		out	std_logic;
+	y55:		out	std_logic;
+	y56:		out	std_logic;
+	y57:		out	std_logic;
+	y58:		out	std_logic;
+	y59:		out	std_logic;
+	y60:		out	std_logic;
+	y61:		out	std_logic;
+	y62:		out	std_logic;
+	y63:		out	std_logic;
+	y64:		out	std_logic;
+	y65:		out	std_logic;
+	y66:		out	std_logic;
+	y67:		out	std_logic;
+	y68:		out	std_logic;
+	y69:		out	std_logic;
+	y70:		out	std_logic;
+	y71:		out	std_logic;
+	y72:		out	std_logic;
+	y73:		out	std_logic;
+	y74:		out	std_logic;
+	y75:		out	std_logic;
+	y76:		out	std_logic;
+	y77:		out	std_logic;
+	y78:		out	std_logic;
+	y79:		out	std_logic;
+	y80:		out	std_logic;
+	y81:		out	std_logic;
+	y82:		out	std_logic;
+	y83:		out	std_logic;
+	y84:		out	std_logic;
+	y85:		out	std_logic;
+	y86:		out	std_logic;
+	y87:		out	std_logic;
+	y88:		out	std_logic;
+	y89:		out	std_logic;
+	y90:		out	std_logic;
+	y91:		out	std_logic;
+	y92:		out	std_logic;
+	y93:		out	std_logic;
+	y94:		out	std_logic;
+	y95:		out	std_logic;
+	y96:		out	std_logic;
+	y97:		out	std_logic;
+	y98:		out	std_logic;
+	y99:		out	std_logic;
+	y100:		out	std_logic;
+	y101:		out	std_logic;
+	y102:		out	std_logic;
+	y103:		out	std_logic;
+	y104:		out	std_logic;
+	y105:		out	std_logic;
+	y106:		out	std_logic;
+	y107:		out	std_logic;
+	y108:		out	std_logic;
+	y109:		out	std_logic;
+	y110:		out	std_logic;
+	y111:		out	std_logic;
+	y112:		out	std_logic;
+	y113:		out	std_logic;
+	y114:		out	std_logic;
+	y115:		out	std_logic;
+	y116:		out	std_logic;
+	y117:		out	std_logic;
+	y118:		out	std_logic;
+	y119:		out	std_logic;
+	y120:		out	std_logic;
+	y121:		out	std_logic;
+	y122:		out	std_logic;
+	y123:		out	std_logic;
+	y124:		out	std_logic;
+	y125:		out	std_logic;
+	y126:		out	std_logic;
+	y127:		out	std_logic;
+	address:	in	std_logic_vector(6 downto 0)
+);
+end;
+
+architecture struct_decoder1x128 of decoder1x128 is
+begin
+	y0		<= data when address = "0000000" else '0';
+	y1		<= data when address = "0000001" else '0';
+	y2		<= data when address = "0000010" else '0';
+	y3		<= data when address = "0000011" else '0';
+	y4		<= data when address = "0000100" else '0';
+	y5		<= data when address = "0000101" else '0';
+	y6		<= data when address = "0000110" else '0';
+	y7		<= data when address = "0000111" else '0';
+	y8		<= data when address = "0001000" else '0';
+	y9		<= data when address = "0001001" else '0';
+	y10		<= data when address = "0001010" else '0';
+	y11		<= data when address = "0001011" else '0';
+	y12		<= data when address = "0001100" else '0';
+	y13		<= data when address = "0001101" else '0';
+	y14		<= data when address = "0001110" else '0';
+	y15		<= data when address = "0001111" else '0';
+	y16		<= data when address = "0010000" else '0';
+	y17		<= data when address = "0010001" else '0';
+	y18		<= data when address = "0010010" else '0';
+	y19		<= data when address = "0010011" else '0';
+	y20		<= data when address = "0010100" else '0';
+	y21		<= data when address = "0010101" else '0';
+	y22		<= data when address = "0010110" else '0';
+	y23		<= data when address = "0010111" else '0';
+	y24		<= data when address = "0011000" else '0';
+	y25		<= data when address = "0011001" else '0';
+	y26		<= data when address = "0011010" else '0';
+	y27		<= data when address = "0011011" else '0';
+	y28		<= data when address = "0011100" else '0';
+	y29		<= data when address = "0011101" else '0';
+	y30		<= data when address = "0011110" else '0';
+	y31		<= data when address = "0011111" else '0';
+	y32		<= data when address = "0100000" else '0';
+	y33		<= data when address = "0100001" else '0';
+	y34		<= data when address = "0100010" else '0';
+	y35		<= data when address = "0100011" else '0';
+	y36		<= data when address = "0100100" else '0';
+	y37		<= data when address = "0100101" else '0';
+	y38		<= data when address = "0100110" else '0';
+	y39		<= data when address = "0100111" else '0';
+	y40		<= data when address = "0101000" else '0';
+	y41		<= data when address = "0101001" else '0';
+	y42		<= data when address = "0101010" else '0';
+	y43		<= data when address = "0101011" else '0';
+	y44		<= data when address = "0101100" else '0';
+	y45		<= data when address = "0101101" else '0';
+	y46		<= data when address = "0101110" else '0';
+	y47		<= data when address = "0101111" else '0';
+	y48		<= data when address = "0110000" else '0';
+	y49		<= data when address = "0110001" else '0';
+	y50		<= data when address = "0110010" else '0';
+	y51		<= data when address = "0110011" else '0';
+	y52		<= data when address = "0110100" else '0';
+	y53		<= data when address = "0110101" else '0';
+	y54		<= data when address = "0110110" else '0';
+	y55		<= data when address = "0110111" else '0';
+	y56		<= data when address = "0111000" else '0';
+	y57		<= data when address = "0111001" else '0';
+	y58		<= data when address = "0111010" else '0';
+	y59		<= data when address = "0111011" else '0';
+	y60		<= data when address = "0111100" else '0';
+	y61		<= data when address = "0111101" else '0';
+	y62		<= data when address = "0111110" else '0';
+	y63		<= data when address = "0111111" else '0';
+	y64		<= data when address = "1000000" else '0';
+	y65		<= data when address = "1000001" else '0';
+	y66		<= data when address = "1000010" else '0';
+	y67		<= data when address = "1000011" else '0';
+	y68		<= data when address = "1000100" else '0';
+	y69		<= data when address = "1000101" else '0';
+	y70		<= data when address = "1000110" else '0';
+	y71		<= data when address = "1000111" else '0';
+	y72		<= data when address = "1001000" else '0';
+	y73		<= data when address = "1001001" else '0';
+	y74		<= data when address = "1001010" else '0';
+	y75		<= data when address = "1001011" else '0';
+	y76		<= data when address = "1001100" else '0';
+	y77		<= data when address = "1001101" else '0';
+	y78		<= data when address = "1001110" else '0';
+	y79		<= data when address = "1001111" else '0';
+	y80		<= data when address = "1010000" else '0';
+	y81		<= data when address = "1010001" else '0';
+	y82		<= data when address = "1010010" else '0';
+	y83		<= data when address = "1010011" else '0';
+	y84		<= data when address = "1010100" else '0';
+	y85		<= data when address = "1010101" else '0';
+	y86		<= data when address = "1010110" else '0';
+	y87		<= data when address = "1010111" else '0';
+	y88		<= data when address = "1011000" else '0';
+	y89		<= data when address = "1011001" else '0';
+	y90		<= data when address = "1011010" else '0';
+	y91		<= data when address = "1011011" else '0';
+	y92		<= data when address = "1011100" else '0';
+	y93		<= data when address = "1011101" else '0';
+	y94		<= data when address = "1011110" else '0';
+	y95		<= data when address = "1011111" else '0';
+	y96		<= data when address = "1100000" else '0';
+	y97		<= data when address = "1100001" else '0';
+	y98		<= data when address = "1100010" else '0';
+	y99		<= data when address = "1100011" else '0';
+	y100	<= data when address = "1100100" else '0';
+	y101	<= data when address = "1100101" else '0';
+	y102	<= data when address = "1100110" else '0';
+	y103	<= data when address = "1100111" else '0';
+	y104	<= data when address = "1101000" else '0';
+	y105	<= data when address = "1101001" else '0';
+	y106	<= data when address = "1101010" else '0';
+	y107	<= data when address = "1101011" else '0';
+	y108	<= data when address = "1101100" else '0';
+	y109	<= data when address = "1101101" else '0';
+	y110	<= data when address = "1101110" else '0';
+	y111	<= data when address = "1101111" else '0';
+	y112	<= data when address = "1110000" else '0';
+	y113	<= data when address = "1110001" else '0';
+	y114	<= data when address = "1110010" else '0';
+	y115	<= data when address = "1110011" else '0';
+	y116	<= data when address = "1110100" else '0';
+	y117	<= data when address = "1110101" else '0';
+	y118	<= data when address = "1110110" else '0';
+	y119	<= data when address = "1110111" else '0';
+	y120	<= data when address = "1111000" else '0';
+	y121	<= data when address = "1111001" else '0';
+	y122	<= data when address = "1111010" else '0';
+	y123	<= data when address = "1111011" else '0';
+	y124	<= data when address = "1111100" else '0';
+	y125	<= data when address = "1111101" else '0';
+	y126	<= data when address = "1111110" else '0';
+	y127	<= data when address = "1111111" else '0';
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity decoderNx128 is
+generic(
+	N: positive
+);
+port(
+	data:		in	std_logic_vector((N-1) downto 0);
+	y0:			out	std_logic_vector((N-1) downto 0);
+	y1:			out	std_logic_vector((N-1) downto 0);
+	y2:			out	std_logic_vector((N-1) downto 0);
+	y3:			out	std_logic_vector((N-1) downto 0);
+	y4:			out	std_logic_vector((N-1) downto 0);
+	y5:			out	std_logic_vector((N-1) downto 0);
+	y6:			out	std_logic_vector((N-1) downto 0);
+	y7:			out	std_logic_vector((N-1) downto 0);
+	y8:			out	std_logic_vector((N-1) downto 0);
+	y9:			out	std_logic_vector((N-1) downto 0);
+	y10:		out	std_logic_vector((N-1) downto 0);
+	y11:		out	std_logic_vector((N-1) downto 0);
+	y12:		out	std_logic_vector((N-1) downto 0);
+	y13:		out	std_logic_vector((N-1) downto 0);
+	y14:		out	std_logic_vector((N-1) downto 0);
+	y15:		out	std_logic_vector((N-1) downto 0);
+	y16:		out	std_logic_vector((N-1) downto 0);
+	y17:		out	std_logic_vector((N-1) downto 0);
+	y18:		out	std_logic_vector((N-1) downto 0);
+	y19:		out	std_logic_vector((N-1) downto 0);
+	y20:		out	std_logic_vector((N-1) downto 0);
+	y21:		out	std_logic_vector((N-1) downto 0);
+	y22:		out	std_logic_vector((N-1) downto 0);
+	y23:		out	std_logic_vector((N-1) downto 0);
+	y24:		out	std_logic_vector((N-1) downto 0);
+	y25:		out	std_logic_vector((N-1) downto 0);
+	y26:		out	std_logic_vector((N-1) downto 0);
+	y27:		out	std_logic_vector((N-1) downto 0);
+	y28:		out	std_logic_vector((N-1) downto 0);
+	y29:		out	std_logic_vector((N-1) downto 0);
+	y30:		out	std_logic_vector((N-1) downto 0);
+	y31:		out	std_logic_vector((N-1) downto 0);
+	y32:		out	std_logic_vector((N-1) downto 0);
+	y33:		out	std_logic_vector((N-1) downto 0);
+	y34:		out	std_logic_vector((N-1) downto 0);
+	y35:		out	std_logic_vector((N-1) downto 0);
+	y36:		out	std_logic_vector((N-1) downto 0);
+	y37:		out	std_logic_vector((N-1) downto 0);
+	y38:		out	std_logic_vector((N-1) downto 0);
+	y39:		out	std_logic_vector((N-1) downto 0);
+	y40:		out	std_logic_vector((N-1) downto 0);
+	y41:		out	std_logic_vector((N-1) downto 0);
+	y42:		out	std_logic_vector((N-1) downto 0);
+	y43:		out	std_logic_vector((N-1) downto 0);
+	y44:		out	std_logic_vector((N-1) downto 0);
+	y45:		out	std_logic_vector((N-1) downto 0);
+	y46:		out	std_logic_vector((N-1) downto 0);
+	y47:		out	std_logic_vector((N-1) downto 0);
+	y48:		out	std_logic_vector((N-1) downto 0);
+	y49:		out	std_logic_vector((N-1) downto 0);
+	y50:		out	std_logic_vector((N-1) downto 0);
+	y51:		out	std_logic_vector((N-1) downto 0);
+	y52:		out	std_logic_vector((N-1) downto 0);
+	y53:		out	std_logic_vector((N-1) downto 0);
+	y54:		out	std_logic_vector((N-1) downto 0);
+	y55:		out	std_logic_vector((N-1) downto 0);
+	y56:		out	std_logic_vector((N-1) downto 0);
+	y57:		out	std_logic_vector((N-1) downto 0);
+	y58:		out	std_logic_vector((N-1) downto 0);
+	y59:		out	std_logic_vector((N-1) downto 0);
+	y60:		out	std_logic_vector((N-1) downto 0);
+	y61:		out	std_logic_vector((N-1) downto 0);
+	y62:		out	std_logic_vector((N-1) downto 0);
+	y63:		out	std_logic_vector((N-1) downto 0);
+	y64:		out	std_logic_vector((N-1) downto 0);
+	y65:		out	std_logic_vector((N-1) downto 0);
+	y66:		out	std_logic_vector((N-1) downto 0);
+	y67:		out	std_logic_vector((N-1) downto 0);
+	y68:		out	std_logic_vector((N-1) downto 0);
+	y69:		out	std_logic_vector((N-1) downto 0);
+	y70:		out	std_logic_vector((N-1) downto 0);
+	y71:		out	std_logic_vector((N-1) downto 0);
+	y72:		out	std_logic_vector((N-1) downto 0);
+	y73:		out	std_logic_vector((N-1) downto 0);
+	y74:		out	std_logic_vector((N-1) downto 0);
+	y75:		out	std_logic_vector((N-1) downto 0);
+	y76:		out	std_logic_vector((N-1) downto 0);
+	y77:		out	std_logic_vector((N-1) downto 0);
+	y78:		out	std_logic_vector((N-1) downto 0);
+	y79:		out	std_logic_vector((N-1) downto 0);
+	y80:		out	std_logic_vector((N-1) downto 0);
+	y81:		out	std_logic_vector((N-1) downto 0);
+	y82:		out	std_logic_vector((N-1) downto 0);
+	y83:		out	std_logic_vector((N-1) downto 0);
+	y84:		out	std_logic_vector((N-1) downto 0);
+	y85:		out	std_logic_vector((N-1) downto 0);
+	y86:		out	std_logic_vector((N-1) downto 0);
+	y87:		out	std_logic_vector((N-1) downto 0);
+	y88:		out	std_logic_vector((N-1) downto 0);
+	y89:		out	std_logic_vector((N-1) downto 0);
+	y90:		out	std_logic_vector((N-1) downto 0);
+	y91:		out	std_logic_vector((N-1) downto 0);
+	y92:		out	std_logic_vector((N-1) downto 0);
+	y93:		out	std_logic_vector((N-1) downto 0);
+	y94:		out	std_logic_vector((N-1) downto 0);
+	y95:		out	std_logic_vector((N-1) downto 0);
+	y96:		out	std_logic_vector((N-1) downto 0);
+	y97:		out	std_logic_vector((N-1) downto 0);
+	y98:		out	std_logic_vector((N-1) downto 0);
+	y99:		out	std_logic_vector((N-1) downto 0);
+	y100:		out	std_logic_vector((N-1) downto 0);
+	y101:		out	std_logic_vector((N-1) downto 0);
+	y102:		out	std_logic_vector((N-1) downto 0);
+	y103:		out	std_logic_vector((N-1) downto 0);
+	y104:		out	std_logic_vector((N-1) downto 0);
+	y105:		out	std_logic_vector((N-1) downto 0);
+	y106:		out	std_logic_vector((N-1) downto 0);
+	y107:		out	std_logic_vector((N-1) downto 0);
+	y108:		out	std_logic_vector((N-1) downto 0);
+	y109:		out	std_logic_vector((N-1) downto 0);
+	y110:		out	std_logic_vector((N-1) downto 0);
+	y111:		out	std_logic_vector((N-1) downto 0);
+	y112:		out	std_logic_vector((N-1) downto 0);
+	y113:		out	std_logic_vector((N-1) downto 0);
+	y114:		out	std_logic_vector((N-1) downto 0);
+	y115:		out	std_logic_vector((N-1) downto 0);
+	y116:		out	std_logic_vector((N-1) downto 0);
+	y117:		out	std_logic_vector((N-1) downto 0);
+	y118:		out	std_logic_vector((N-1) downto 0);
+	y119:		out	std_logic_vector((N-1) downto 0);
+	y120:		out	std_logic_vector((N-1) downto 0);
+	y121:		out	std_logic_vector((N-1) downto 0);
+	y122:		out	std_logic_vector((N-1) downto 0);
+	y123:		out	std_logic_vector((N-1) downto 0);
+	y124:		out	std_logic_vector((N-1) downto 0);
+	y125:		out	std_logic_vector((N-1) downto 0);
+	y126:		out	std_logic_vector((N-1) downto 0);
+	y127:		out	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(6 downto 0)
+);
+end;
+
+architecture struct_decoderNx128 of decoderNx128 is
+component decoder1x128 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	y16:		out	std_logic;
+	y17:		out	std_logic;
+	y18:		out	std_logic;
+	y19:		out	std_logic;
+	y20:		out	std_logic;
+	y21:		out	std_logic;
+	y22:		out	std_logic;
+	y23:		out	std_logic;
+	y24:		out	std_logic;
+	y25:		out	std_logic;
+	y26:		out	std_logic;
+	y27:		out	std_logic;
+	y28:		out	std_logic;
+	y29:		out	std_logic;
+	y30:		out	std_logic;
+	y31:		out	std_logic;
+	y32:		out	std_logic;
+	y33:		out	std_logic;
+	y34:		out	std_logic;
+	y35:		out	std_logic;
+	y36:		out	std_logic;
+	y37:		out	std_logic;
+	y38:		out	std_logic;
+	y39:		out	std_logic;
+	y40:		out	std_logic;
+	y41:		out	std_logic;
+	y42:		out	std_logic;
+	y43:		out	std_logic;
+	y44:		out	std_logic;
+	y45:		out	std_logic;
+	y46:		out	std_logic;
+	y47:		out	std_logic;
+	y48:		out	std_logic;
+	y49:		out	std_logic;
+	y50:		out	std_logic;
+	y51:		out	std_logic;
+	y52:		out	std_logic;
+	y53:		out	std_logic;
+	y54:		out	std_logic;
+	y55:		out	std_logic;
+	y56:		out	std_logic;
+	y57:		out	std_logic;
+	y58:		out	std_logic;
+	y59:		out	std_logic;
+	y60:		out	std_logic;
+	y61:		out	std_logic;
+	y62:		out	std_logic;
+	y63:		out	std_logic;
+	y64:		out	std_logic;
+	y65:		out	std_logic;
+	y66:		out	std_logic;
+	y67:		out	std_logic;
+	y68:		out	std_logic;
+	y69:		out	std_logic;
+	y70:		out	std_logic;
+	y71:		out	std_logic;
+	y72:		out	std_logic;
+	y73:		out	std_logic;
+	y74:		out	std_logic;
+	y75:		out	std_logic;
+	y76:		out	std_logic;
+	y77:		out	std_logic;
+	y78:		out	std_logic;
+	y79:		out	std_logic;
+	y80:		out	std_logic;
+	y81:		out	std_logic;
+	y82:		out	std_logic;
+	y83:		out	std_logic;
+	y84:		out	std_logic;
+	y85:		out	std_logic;
+	y86:		out	std_logic;
+	y87:		out	std_logic;
+	y88:		out	std_logic;
+	y89:		out	std_logic;
+	y90:		out	std_logic;
+	y91:		out	std_logic;
+	y92:		out	std_logic;
+	y93:		out	std_logic;
+	y94:		out	std_logic;
+	y95:		out	std_logic;
+	y96:		out	std_logic;
+	y97:		out	std_logic;
+	y98:		out	std_logic;
+	y99:		out	std_logic;
+	y100:		out	std_logic;
+	y101:		out	std_logic;
+	y102:		out	std_logic;
+	y103:		out	std_logic;
+	y104:		out	std_logic;
+	y105:		out	std_logic;
+	y106:		out	std_logic;
+	y107:		out	std_logic;
+	y108:		out	std_logic;
+	y109:		out	std_logic;
+	y110:		out	std_logic;
+	y111:		out	std_logic;
+	y112:		out	std_logic;
+	y113:		out	std_logic;
+	y114:		out	std_logic;
+	y115:		out	std_logic;
+	y116:		out	std_logic;
+	y117:		out	std_logic;
+	y118:		out	std_logic;
+	y119:		out	std_logic;
+	y120:		out	std_logic;
+	y121:		out	std_logic;
+	y122:		out	std_logic;
+	y123:		out	std_logic;
+	y124:		out	std_logic;
+	y125:		out	std_logic;
+	y126:		out	std_logic;
+	y127:		out	std_logic;
+	address:	in	std_logic_vector(6 downto 0)
+);
+
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: decoder1x128 port map(
+			data	=> data(i),
+			y0		=> y0(i),
+			y1		=> y1(i),
+			y2		=> y2(i),
+			y3		=> y3(i),
+			y4		=> y4(i),
+			y5		=> y5(i),
+			y6		=> y6(i),
+			y7		=> y7(i),
+			y8		=> y8(i),
+			y9		=> y9(i),
+			y10		=> y10(i),
+			y11		=> y11(i),
+			y12		=> y12(i),
+			y13		=> y13(i),
+			y14		=> y14(i),
+			y15		=> y15(i),
+			y16		=> y16(i),
+			y17		=> y17(i),
+			y18		=> y18(i),
+			y19		=> y19(i),
+			y20		=> y20(i),
+			y21		=> y21(i),
+			y22		=> y22(i),
+			y23		=> y23(i),
+			y24		=> y24(i),
+			y25		=> y25(i),
+			y26		=> y26(i),
+			y27		=> y27(i),
+			y28		=> y28(i),
+			y29		=> y29(i),
+			y30		=> y30(i),
+			y31		=> y31(i),
+			y32		=> y32(i),
+			y33		=> y33(i),
+			y34		=> y34(i),
+			y35		=> y35(i),
+			y36		=> y36(i),
+			y37		=> y37(i),
+			y38		=> y38(i),
+			y39		=> y39(i),
+			y40		=> y40(i),
+			y41		=> y41(i),
+			y42		=> y42(i),
+			y43		=> y43(i),
+			y44		=> y44(i),
+			y45		=> y45(i),
+			y46		=> y46(i),
+			y47		=> y47(i),
+			y48		=> y48(i),
+			y49		=> y49(i),
+			y50		=> y50(i),
+			y51		=> y51(i),
+			y52		=> y52(i),
+			y53		=> y53(i),
+			y54		=> y54(i),
+			y55		=> y55(i),
+			y56		=> y56(i),
+			y57		=> y57(i),
+			y58		=> y58(i),
+			y59		=> y59(i),
+			y60		=> y60(i),
+			y61		=> y61(i),
+			y62		=> y62(i),
+			y63		=> y63(i),
+			y64		=> y64(i),
+			y65		=> y65(i),
+			y66		=> y66(i),
+			y67		=> y67(i),
+			y68		=> y68(i),
+			y69		=> y69(i),
+			y70		=> y70(i),
+			y71		=> y71(i),
+			y72		=> y72(i),
+			y73		=> y73(i),
+			y74		=> y74(i),
+			y75		=> y75(i),
+			y76		=> y76(i),
+			y77		=> y77(i),
+			y78		=> y78(i),
+			y79		=> y79(i),
+			y80		=> y80(i),
+			y81		=> y81(i),
+			y82		=> y82(i),
+			y83		=> y83(i),
+			y84		=> y84(i),
+			y85		=> y85(i),
+			y86		=> y86(i),
+			y87		=> y87(i),
+			y88		=> y88(i),
+			y89		=> y89(i),
+			y90		=> y90(i),
+			y91		=> y91(i),
+			y92		=> y92(i),
+			y93		=> y93(i),
+			y94		=> y94(i),
+			y95		=> y95(i),
+			y96		=> y96(i),
+			y97		=> y97(i),
+			y98		=> y98(i),
+			y99		=> y99(i),
+			y100	=> y100(i),
+			y101	=> y101(i),
+			y102	=> y102(i),
+			y103	=> y103(i),
+			y104	=> y104(i),
+			y105	=> y105(i),
+			y106	=> y106(i),
+			y107	=> y107(i),
+			y108	=> y108(i),
+			y109	=> y109(i),
+			y110	=> y110(i),
+			y111	=> y111(i),
+			y112	=> y112(i),
+			y113	=> y113(i),
+			y114	=> y114(i),
+			y115	=> y115(i),
+			y116	=> y116(i),
+			y117	=> y117(i),
+			y118	=> y118(i),
+			y119	=> y119(i),
+			y120	=> y120(i),
+			y121	=> y121(i),
+			y122	=> y122(i),
+			y123	=> y123(i),
+			y124	=> y124(i),
+			y125	=> y125(i),
+			y126	=> y126(i),
+			y127	=> y127(i),
+			address	=> address
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity encoder256x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	data8:		in	std_logic;
+	data9:		in	std_logic;
+	data10:		in	std_logic;
+	data11:		in	std_logic;
+	data12:		in	std_logic;
+	data13:		in	std_logic;
+	data14:		in	std_logic;
+	data15:		in	std_logic;
+	data16:		in	std_logic;
+	data17:		in	std_logic;
+	data18:		in	std_logic;
+	data19:		in	std_logic;
+	data20:		in	std_logic;
+	data21:		in	std_logic;
+	data22:		in	std_logic;
+	data23:		in	std_logic;
+	data24:		in	std_logic;
+	data25:		in	std_logic;
+	data26:		in	std_logic;
+	data27:		in	std_logic;
+	data28:		in	std_logic;
+	data29:		in	std_logic;
+	data30:		in	std_logic;
+	data31:		in	std_logic;
+	data32:		in	std_logic;
+	data33:		in	std_logic;
+	data34:		in	std_logic;
+	data35:		in	std_logic;
+	data36:		in	std_logic;
+	data37:		in	std_logic;
+	data38:		in	std_logic;
+	data39:		in	std_logic;
+	data40:		in	std_logic;
+	data41:		in	std_logic;
+	data42:		in	std_logic;
+	data43:		in	std_logic;
+	data44:		in	std_logic;
+	data45:		in	std_logic;
+	data46:		in	std_logic;
+	data47:		in	std_logic;
+	data48:		in	std_logic;
+	data49:		in	std_logic;
+	data50:		in	std_logic;
+	data51:		in	std_logic;
+	data52:		in	std_logic;
+	data53:		in	std_logic;
+	data54:		in	std_logic;
+	data55:		in	std_logic;
+	data56:		in	std_logic;
+	data57:		in	std_logic;
+	data58:		in	std_logic;
+	data59:		in	std_logic;
+	data60:		in	std_logic;
+	data61:		in	std_logic;
+	data62:		in	std_logic;
+	data63:		in	std_logic;
+	data64:		in	std_logic;
+	data65:		in	std_logic;
+	data66:		in	std_logic;
+	data67:		in	std_logic;
+	data68:		in	std_logic;
+	data69:		in	std_logic;
+	data70:		in	std_logic;
+	data71:		in	std_logic;
+	data72:		in	std_logic;
+	data73:		in	std_logic;
+	data74:		in	std_logic;
+	data75:		in	std_logic;
+	data76:		in	std_logic;
+	data77:		in	std_logic;
+	data78:		in	std_logic;
+	data79:		in	std_logic;
+	data80:		in	std_logic;
+	data81:		in	std_logic;
+	data82:		in	std_logic;
+	data83:		in	std_logic;
+	data84:		in	std_logic;
+	data85:		in	std_logic;
+	data86:		in	std_logic;
+	data87:		in	std_logic;
+	data88:		in	std_logic;
+	data89:		in	std_logic;
+	data90:		in	std_logic;
+	data91:		in	std_logic;
+	data92:		in	std_logic;
+	data93:		in	std_logic;
+	data94:		in	std_logic;
+	data95:		in	std_logic;
+	data96:		in	std_logic;
+	data97:		in	std_logic;
+	data98:		in	std_logic;
+	data99:		in	std_logic;
+	data100:	in	std_logic;
+	data101:	in	std_logic;
+	data102:	in	std_logic;
+	data103:	in	std_logic;
+	data104:	in	std_logic;
+	data105:	in	std_logic;
+	data106:	in	std_logic;
+	data107:	in	std_logic;
+	data108:	in	std_logic;
+	data109:	in	std_logic;
+	data110:	in	std_logic;
+	data111:	in	std_logic;
+	data112:	in	std_logic;
+	data113:	in	std_logic;
+	data114:	in	std_logic;
+	data115:	in	std_logic;
+	data116:	in	std_logic;
+	data117:	in	std_logic;
+	data118:	in	std_logic;
+	data119:	in	std_logic;
+	data120:	in	std_logic;
+	data121:	in	std_logic;
+	data122:	in	std_logic;
+	data123:	in	std_logic;
+	data124:	in	std_logic;
+	data125:	in	std_logic;
+	data126:	in	std_logic;
+	data127:	in	std_logic;
+	data128:	in	std_logic;
+	data129:	in	std_logic;
+	data130:	in	std_logic;
+	data131:	in	std_logic;
+	data132:	in	std_logic;
+	data133:	in	std_logic;
+	data134:	in	std_logic;
+	data135:	in	std_logic;
+	data136:	in	std_logic;
+	data137:	in	std_logic;
+	data138:	in	std_logic;
+	data139:	in	std_logic;
+	data140:	in	std_logic;
+	data141:	in	std_logic;
+	data142:	in	std_logic;
+	data143:	in	std_logic;
+	data144:	in	std_logic;
+	data145:	in	std_logic;
+	data146:	in	std_logic;
+	data147:	in	std_logic;
+	data148:	in	std_logic;
+	data149:	in	std_logic;
+	data150:	in	std_logic;
+	data151:	in	std_logic;
+	data152:	in	std_logic;
+	data153:	in	std_logic;
+	data154:	in	std_logic;
+	data155:	in	std_logic;
+	data156:	in	std_logic;
+	data157:	in	std_logic;
+	data158:	in	std_logic;
+	data159:	in	std_logic;
+	data160:	in	std_logic;
+	data161:	in	std_logic;
+	data162:	in	std_logic;
+	data163:	in	std_logic;
+	data164:	in	std_logic;
+	data165:	in	std_logic;
+	data166:	in	std_logic;
+	data167:	in	std_logic;
+	data168:	in	std_logic;
+	data169:	in	std_logic;
+	data170:	in	std_logic;
+	data171:	in	std_logic;
+	data172:	in	std_logic;
+	data173:	in	std_logic;
+	data174:	in	std_logic;
+	data175:	in	std_logic;
+	data176:	in	std_logic;
+	data177:	in	std_logic;
+	data178:	in	std_logic;
+	data179:	in	std_logic;
+	data180:	in	std_logic;
+	data181:	in	std_logic;
+	data182:	in	std_logic;
+	data183:	in	std_logic;
+	data184:	in	std_logic;
+	data185:	in	std_logic;
+	data186:	in	std_logic;
+	data187:	in	std_logic;
+	data188:	in	std_logic;
+	data189:	in	std_logic;
+	data190:	in	std_logic;
+	data191:	in	std_logic;
+	data192:	in	std_logic;
+	data193:	in	std_logic;
+	data194:	in	std_logic;
+	data195:	in	std_logic;
+	data196:	in	std_logic;
+	data197:	in	std_logic;
+	data198:	in	std_logic;
+	data199:	in	std_logic;
+	data200:	in	std_logic;
+	data201:	in	std_logic;
+	data202:	in	std_logic;
+	data203:	in	std_logic;
+	data204:	in	std_logic;
+	data205:	in	std_logic;
+	data206:	in	std_logic;
+	data207:	in	std_logic;
+	data208:	in	std_logic;
+	data209:	in	std_logic;
+	data210:	in	std_logic;
+	data211:	in	std_logic;
+	data212:	in	std_logic;
+	data213:	in	std_logic;
+	data214:	in	std_logic;
+	data215:	in	std_logic;
+	data216:	in	std_logic;
+	data217:	in	std_logic;
+	data218:	in	std_logic;
+	data219:	in	std_logic;
+	data220:	in	std_logic;
+	data221:	in	std_logic;
+	data222:	in	std_logic;
+	data223:	in	std_logic;
+	data224:	in	std_logic;
+	data225:	in	std_logic;
+	data226:	in	std_logic;
+	data227:	in	std_logic;
+	data228:	in	std_logic;
+	data229:	in	std_logic;
+	data230:	in	std_logic;
+	data231:	in	std_logic;
+	data232:	in	std_logic;
+	data233:	in	std_logic;
+	data234:	in	std_logic;
+	data235:	in	std_logic;
+	data236:	in	std_logic;
+	data237:	in	std_logic;
+	data238:	in	std_logic;
+	data239:	in	std_logic;
+	data240:	in	std_logic;
+	data241:	in	std_logic;
+	data242:	in	std_logic;
+	data243:	in	std_logic;
+	data244:	in	std_logic;
+	data245:	in	std_logic;
+	data246:	in	std_logic;
+	data247:	in	std_logic;
+	data248:	in	std_logic;
+	data249:	in	std_logic;
+	data250:	in	std_logic;
+	data251:	in	std_logic;
+	data252:	in	std_logic;
+	data253:	in	std_logic;
+	data254:	in	std_logic;
+	data255:	in	std_logic;
+	address:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic
+);
+end;
+
+architecture struct_encoder256x1 of encoder256x1 is
+begin
+	with address select
+		output <=
+			data0	when "00000000",
+			data1	when "00000001",
+			data2	when "00000010",
+			data3	when "00000011",
+			data4	when "00000100",
+			data5	when "00000101",
+			data6	when "00000110",
+			data7	when "00000111",
+			data8	when "00001000",
+			data9	when "00001001",
+			data10	when "00001010",
+			data11	when "00001011",
+			data12	when "00001100",
+			data13	when "00001101",
+			data14	when "00001110",
+			data15	when "00001111",
+			data16	when "00010000",
+			data17	when "00010001",
+			data18	when "00010010",
+			data19	when "00010011",
+			data20	when "00010100",
+			data21	when "00010101",
+			data22	when "00010110",
+			data23	when "00010111",
+			data24	when "00011000",
+			data25	when "00011001",
+			data26	when "00011010",
+			data27	when "00011011",
+			data28	when "00011100",
+			data29	when "00011101",
+			data30	when "00011110",
+			data31	when "00011111",
+			data32	when "00100000",
+			data33	when "00100001",
+			data34	when "00100010",
+			data35	when "00100011",
+			data36	when "00100100",
+			data37	when "00100101",
+			data38	when "00100110",
+			data39	when "00100111",
+			data40	when "00101000",
+			data41	when "00101001",
+			data42	when "00101010",
+			data43	when "00101011",
+			data44	when "00101100",
+			data45	when "00101101",
+			data46	when "00101110",
+			data47	when "00101111",
+			data48	when "00110000",
+			data49	when "00110001",
+			data50	when "00110010",
+			data51	when "00110011",
+			data52	when "00110100",
+			data53	when "00110101",
+			data54	when "00110110",
+			data55	when "00110111",
+			data56	when "00111000",
+			data57	when "00111001",
+			data58	when "00111010",
+			data59	when "00111011",
+			data60	when "00111100",
+			data61	when "00111101",
+			data62	when "00111110",
+			data63	when "00111111",
+			data64	when "01000000",
+			data65	when "01000001",
+			data66	when "01000010",
+			data67	when "01000011",
+			data68	when "01000100",
+			data69	when "01000101",
+			data70	when "01000110",
+			data71	when "01000111",
+			data72	when "01001000",
+			data73	when "01001001",
+			data74	when "01001010",
+			data75	when "01001011",
+			data76	when "01001100",
+			data77	when "01001101",
+			data78	when "01001110",
+			data79	when "01001111",
+			data80	when "01010000",
+			data81	when "01010001",
+			data82	when "01010010",
+			data83	when "01010011",
+			data84	when "01010100",
+			data85	when "01010101",
+			data86	when "01010110",
+			data87	when "01010111",
+			data88	when "01011000",
+			data89	when "01011001",
+			data90	when "01011010",
+			data91	when "01011011",
+			data92	when "01011100",
+			data93	when "01011101",
+			data94	when "01011110",
+			data95	when "01011111",
+			data96	when "01100000",
+			data97	when "01100001",
+			data98	when "01100010",
+			data99	when "01100011",
+			data100	when "01100100",
+			data101	when "01100101",
+			data102	when "01100110",
+			data103	when "01100111",
+			data104	when "01101000",
+			data105	when "01101001",
+			data106	when "01101010",
+			data107	when "01101011",
+			data108	when "01101100",
+			data109	when "01101101",
+			data110	when "01101110",
+			data111	when "01101111",
+			data112	when "01110000",
+			data113	when "01110001",
+			data114	when "01110010",
+			data115	when "01110011",
+			data116	when "01110100",
+			data117	when "01110101",
+			data118	when "01110110",
+			data119	when "01110111",
+			data120	when "01111000",
+			data121	when "01111001",
+			data122	when "01111010",
+			data123	when "01111011",
+			data124	when "01111100",
+			data125	when "01111101",
+			data126	when "01111110",
+			data127	when "01111111",
+			data128	when "10000000",
+			data129	when "10000001",
+			data130	when "10000010",
+			data131	when "10000011",
+			data132	when "10000100",
+			data133	when "10000101",
+			data134	when "10000110",
+			data135	when "10000111",
+			data136	when "10001000",
+			data137	when "10001001",
+			data138	when "10001010",
+			data139	when "10001011",
+			data140	when "10001100",
+			data141	when "10001101",
+			data142	when "10001110",
+			data143	when "10001111",
+			data144	when "10010000",
+			data145	when "10010001",
+			data146	when "10010010",
+			data147	when "10010011",
+			data148	when "10010100",
+			data149	when "10010101",
+			data150	when "10010110",
+			data151	when "10010111",
+			data152	when "10011000",
+			data153	when "10011001",
+			data154	when "10011010",
+			data155	when "10011011",
+			data156	when "10011100",
+			data157	when "10011101",
+			data158	when "10011110",
+			data159	when "10011111",
+			data160	when "10100000",
+			data161	when "10100001",
+			data162	when "10100010",
+			data163	when "10100011",
+			data164	when "10100100",
+			data165	when "10100101",
+			data166	when "10100110",
+			data167	when "10100111",
+			data168	when "10101000",
+			data169	when "10101001",
+			data170	when "10101010",
+			data171	when "10101011",
+			data172	when "10101100",
+			data173	when "10101101",
+			data174	when "10101110",
+			data175	when "10101111",
+			data176	when "10110000",
+			data177	when "10110001",
+			data178	when "10110010",
+			data179	when "10110011",
+			data180	when "10110100",
+			data181	when "10110101",
+			data182	when "10110110",
+			data183	when "10110111",
+			data184	when "10111000",
+			data185	when "10111001",
+			data186	when "10111010",
+			data187	when "10111011",
+			data188	when "10111100",
+			data189	when "10111101",
+			data190	when "10111110",
+			data191	when "10111111",
+			data192	when "11000000",
+			data193	when "11000001",
+			data194	when "11000010",
+			data195	when "11000011",
+			data196	when "11000100",
+			data197	when "11000101",
+			data198	when "11000110",
+			data199	when "11000111",
+			data200	when "11001000",
+			data201	when "11001001",
+			data202	when "11001010",
+			data203	when "11001011",
+			data204	when "11001100",
+			data205	when "11001101",
+			data206	when "11001110",
+			data207	when "11001111",
+			data208	when "11010000",
+			data209	when "11010001",
+			data210	when "11010010",
+			data211	when "11010011",
+			data212	when "11010100",
+			data213	when "11010101",
+			data214	when "11010110",
+			data215	when "11010111",
+			data216	when "11011000",
+			data217	when "11011001",
+			data218	when "11011010",
+			data219	when "11011011",
+			data220	when "11011100",
+			data221	when "11011101",
+			data222	when "11011110",
+			data223	when "11011111",
+			data224	when "11100000",
+			data225	when "11100001",
+			data226	when "11100010",
+			data227	when "11100011",
+			data228	when "11100100",
+			data229	when "11100101",
+			data230	when "11100110",
+			data231	when "11100111",
+			data232	when "11101000",
+			data233	when "11101001",
+			data234	when "11101010",
+			data235	when "11101011",
+			data236	when "11101100",
+			data237	when "11101101",
+			data238	when "11101110",
+			data239	when "11101111",
+			data240	when "11110000",
+			data241	when "11110001",
+			data242	when "11110010",
+			data243	when "11110011",
+			data244	when "11110100",
+			data245	when "11110101",
+			data246	when "11110110",
+			data247	when "11110111",
+			data248	when "11111000",
+			data249	when "11111001",
+			data250	when "11111010",
+			data251	when "11111011",
+			data252	when "11111100",
+			data253	when "11111101",
+			data254	when "11111110",
+			data255	when "11111111",
+			'0' when others;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity encoder256xN is
+generic(
+	N:	positive
+);
+port(
+	data0:		in	std_logic_vector((N-1) downto 0);
+	data1:		in	std_logic_vector((N-1) downto 0);
+	data2:		in	std_logic_vector((N-1) downto 0);
+	data3:		in	std_logic_vector((N-1) downto 0);
+	data4:		in	std_logic_vector((N-1) downto 0);
+	data5:		in	std_logic_vector((N-1) downto 0);
+	data6:		in	std_logic_vector((N-1) downto 0);
+	data7:		in	std_logic_vector((N-1) downto 0);
+	data8:		in	std_logic_vector((N-1) downto 0);
+	data9:		in	std_logic_vector((N-1) downto 0);
+	data10:		in	std_logic_vector((N-1) downto 0);
+	data11:		in	std_logic_vector((N-1) downto 0);
+	data12:		in	std_logic_vector((N-1) downto 0);
+	data13:		in	std_logic_vector((N-1) downto 0);
+	data14:		in	std_logic_vector((N-1) downto 0);
+	data15:		in	std_logic_vector((N-1) downto 0);
+	data16:		in	std_logic_vector((N-1) downto 0);
+	data17:		in	std_logic_vector((N-1) downto 0);
+	data18:		in	std_logic_vector((N-1) downto 0);
+	data19:		in	std_logic_vector((N-1) downto 0);
+	data20:		in	std_logic_vector((N-1) downto 0);
+	data21:		in	std_logic_vector((N-1) downto 0);
+	data22:		in	std_logic_vector((N-1) downto 0);
+	data23:		in	std_logic_vector((N-1) downto 0);
+	data24:		in	std_logic_vector((N-1) downto 0);
+	data25:		in	std_logic_vector((N-1) downto 0);
+	data26:		in	std_logic_vector((N-1) downto 0);
+	data27:		in	std_logic_vector((N-1) downto 0);
+	data28:		in	std_logic_vector((N-1) downto 0);
+	data29:		in	std_logic_vector((N-1) downto 0);
+	data30:		in	std_logic_vector((N-1) downto 0);
+	data31:		in	std_logic_vector((N-1) downto 0);
+	data32:		in	std_logic_vector((N-1) downto 0);
+	data33:		in	std_logic_vector((N-1) downto 0);
+	data34:		in	std_logic_vector((N-1) downto 0);
+	data35:		in	std_logic_vector((N-1) downto 0);
+	data36:		in	std_logic_vector((N-1) downto 0);
+	data37:		in	std_logic_vector((N-1) downto 0);
+	data38:		in	std_logic_vector((N-1) downto 0);
+	data39:		in	std_logic_vector((N-1) downto 0);
+	data40:		in	std_logic_vector((N-1) downto 0);
+	data41:		in	std_logic_vector((N-1) downto 0);
+	data42:		in	std_logic_vector((N-1) downto 0);
+	data43:		in	std_logic_vector((N-1) downto 0);
+	data44:		in	std_logic_vector((N-1) downto 0);
+	data45:		in	std_logic_vector((N-1) downto 0);
+	data46:		in	std_logic_vector((N-1) downto 0);
+	data47:		in	std_logic_vector((N-1) downto 0);
+	data48:		in	std_logic_vector((N-1) downto 0);
+	data49:		in	std_logic_vector((N-1) downto 0);
+	data50:		in	std_logic_vector((N-1) downto 0);
+	data51:		in	std_logic_vector((N-1) downto 0);
+	data52:		in	std_logic_vector((N-1) downto 0);
+	data53:		in	std_logic_vector((N-1) downto 0);
+	data54:		in	std_logic_vector((N-1) downto 0);
+	data55:		in	std_logic_vector((N-1) downto 0);
+	data56:		in	std_logic_vector((N-1) downto 0);
+	data57:		in	std_logic_vector((N-1) downto 0);
+	data58:		in	std_logic_vector((N-1) downto 0);
+	data59:		in	std_logic_vector((N-1) downto 0);
+	data60:		in	std_logic_vector((N-1) downto 0);
+	data61:		in	std_logic_vector((N-1) downto 0);
+	data62:		in	std_logic_vector((N-1) downto 0);
+	data63:		in	std_logic_vector((N-1) downto 0);
+	data64:		in	std_logic_vector((N-1) downto 0);
+	data65:		in	std_logic_vector((N-1) downto 0);
+	data66:		in	std_logic_vector((N-1) downto 0);
+	data67:		in	std_logic_vector((N-1) downto 0);
+	data68:		in	std_logic_vector((N-1) downto 0);
+	data69:		in	std_logic_vector((N-1) downto 0);
+	data70:		in	std_logic_vector((N-1) downto 0);
+	data71:		in	std_logic_vector((N-1) downto 0);
+	data72:		in	std_logic_vector((N-1) downto 0);
+	data73:		in	std_logic_vector((N-1) downto 0);
+	data74:		in	std_logic_vector((N-1) downto 0);
+	data75:		in	std_logic_vector((N-1) downto 0);
+	data76:		in	std_logic_vector((N-1) downto 0);
+	data77:		in	std_logic_vector((N-1) downto 0);
+	data78:		in	std_logic_vector((N-1) downto 0);
+	data79:		in	std_logic_vector((N-1) downto 0);
+	data80:		in	std_logic_vector((N-1) downto 0);
+	data81:		in	std_logic_vector((N-1) downto 0);
+	data82:		in	std_logic_vector((N-1) downto 0);
+	data83:		in	std_logic_vector((N-1) downto 0);
+	data84:		in	std_logic_vector((N-1) downto 0);
+	data85:		in	std_logic_vector((N-1) downto 0);
+	data86:		in	std_logic_vector((N-1) downto 0);
+	data87:		in	std_logic_vector((N-1) downto 0);
+	data88:		in	std_logic_vector((N-1) downto 0);
+	data89:		in	std_logic_vector((N-1) downto 0);
+	data90:		in	std_logic_vector((N-1) downto 0);
+	data91:		in	std_logic_vector((N-1) downto 0);
+	data92:		in	std_logic_vector((N-1) downto 0);
+	data93:		in	std_logic_vector((N-1) downto 0);
+	data94:		in	std_logic_vector((N-1) downto 0);
+	data95:		in	std_logic_vector((N-1) downto 0);
+	data96:		in	std_logic_vector((N-1) downto 0);
+	data97:		in	std_logic_vector((N-1) downto 0);
+	data98:		in	std_logic_vector((N-1) downto 0);
+	data99:		in	std_logic_vector((N-1) downto 0);
+	data100:	in	std_logic_vector((N-1) downto 0);
+	data101:	in	std_logic_vector((N-1) downto 0);
+	data102:	in	std_logic_vector((N-1) downto 0);
+	data103:	in	std_logic_vector((N-1) downto 0);
+	data104:	in	std_logic_vector((N-1) downto 0);
+	data105:	in	std_logic_vector((N-1) downto 0);
+	data106:	in	std_logic_vector((N-1) downto 0);
+	data107:	in	std_logic_vector((N-1) downto 0);
+	data108:	in	std_logic_vector((N-1) downto 0);
+	data109:	in	std_logic_vector((N-1) downto 0);
+	data110:	in	std_logic_vector((N-1) downto 0);
+	data111:	in	std_logic_vector((N-1) downto 0);
+	data112:	in	std_logic_vector((N-1) downto 0);
+	data113:	in	std_logic_vector((N-1) downto 0);
+	data114:	in	std_logic_vector((N-1) downto 0);
+	data115:	in	std_logic_vector((N-1) downto 0);
+	data116:	in	std_logic_vector((N-1) downto 0);
+	data117:	in	std_logic_vector((N-1) downto 0);
+	data118:	in	std_logic_vector((N-1) downto 0);
+	data119:	in	std_logic_vector((N-1) downto 0);
+	data120:	in	std_logic_vector((N-1) downto 0);
+	data121:	in	std_logic_vector((N-1) downto 0);
+	data122:	in	std_logic_vector((N-1) downto 0);
+	data123:	in	std_logic_vector((N-1) downto 0);
+	data124:	in	std_logic_vector((N-1) downto 0);
+	data125:	in	std_logic_vector((N-1) downto 0);
+	data126:	in	std_logic_vector((N-1) downto 0);
+	data127:	in	std_logic_vector((N-1) downto 0);
+	data128:	in	std_logic_vector((N-1) downto 0);
+	data129:	in	std_logic_vector((N-1) downto 0);
+	data130:	in	std_logic_vector((N-1) downto 0);
+	data131:	in	std_logic_vector((N-1) downto 0);
+	data132:	in	std_logic_vector((N-1) downto 0);
+	data133:	in	std_logic_vector((N-1) downto 0);
+	data134:	in	std_logic_vector((N-1) downto 0);
+	data135:	in	std_logic_vector((N-1) downto 0);
+	data136:	in	std_logic_vector((N-1) downto 0);
+	data137:	in	std_logic_vector((N-1) downto 0);
+	data138:	in	std_logic_vector((N-1) downto 0);
+	data139:	in	std_logic_vector((N-1) downto 0);
+	data140:	in	std_logic_vector((N-1) downto 0);
+	data141:	in	std_logic_vector((N-1) downto 0);
+	data142:	in	std_logic_vector((N-1) downto 0);
+	data143:	in	std_logic_vector((N-1) downto 0);
+	data144:	in	std_logic_vector((N-1) downto 0);
+	data145:	in	std_logic_vector((N-1) downto 0);
+	data146:	in	std_logic_vector((N-1) downto 0);
+	data147:	in	std_logic_vector((N-1) downto 0);
+	data148:	in	std_logic_vector((N-1) downto 0);
+	data149:	in	std_logic_vector((N-1) downto 0);
+	data150:	in	std_logic_vector((N-1) downto 0);
+	data151:	in	std_logic_vector((N-1) downto 0);
+	data152:	in	std_logic_vector((N-1) downto 0);
+	data153:	in	std_logic_vector((N-1) downto 0);
+	data154:	in	std_logic_vector((N-1) downto 0);
+	data155:	in	std_logic_vector((N-1) downto 0);
+	data156:	in	std_logic_vector((N-1) downto 0);
+	data157:	in	std_logic_vector((N-1) downto 0);
+	data158:	in	std_logic_vector((N-1) downto 0);
+	data159:	in	std_logic_vector((N-1) downto 0);
+	data160:	in	std_logic_vector((N-1) downto 0);
+	data161:	in	std_logic_vector((N-1) downto 0);
+	data162:	in	std_logic_vector((N-1) downto 0);
+	data163:	in	std_logic_vector((N-1) downto 0);
+	data164:	in	std_logic_vector((N-1) downto 0);
+	data165:	in	std_logic_vector((N-1) downto 0);
+	data166:	in	std_logic_vector((N-1) downto 0);
+	data167:	in	std_logic_vector((N-1) downto 0);
+	data168:	in	std_logic_vector((N-1) downto 0);
+	data169:	in	std_logic_vector((N-1) downto 0);
+	data170:	in	std_logic_vector((N-1) downto 0);
+	data171:	in	std_logic_vector((N-1) downto 0);
+	data172:	in	std_logic_vector((N-1) downto 0);
+	data173:	in	std_logic_vector((N-1) downto 0);
+	data174:	in	std_logic_vector((N-1) downto 0);
+	data175:	in	std_logic_vector((N-1) downto 0);
+	data176:	in	std_logic_vector((N-1) downto 0);
+	data177:	in	std_logic_vector((N-1) downto 0);
+	data178:	in	std_logic_vector((N-1) downto 0);
+	data179:	in	std_logic_vector((N-1) downto 0);
+	data180:	in	std_logic_vector((N-1) downto 0);
+	data181:	in	std_logic_vector((N-1) downto 0);
+	data182:	in	std_logic_vector((N-1) downto 0);
+	data183:	in	std_logic_vector((N-1) downto 0);
+	data184:	in	std_logic_vector((N-1) downto 0);
+	data185:	in	std_logic_vector((N-1) downto 0);
+	data186:	in	std_logic_vector((N-1) downto 0);
+	data187:	in	std_logic_vector((N-1) downto 0);
+	data188:	in	std_logic_vector((N-1) downto 0);
+	data189:	in	std_logic_vector((N-1) downto 0);
+	data190:	in	std_logic_vector((N-1) downto 0);
+	data191:	in	std_logic_vector((N-1) downto 0);
+	data192:	in	std_logic_vector((N-1) downto 0);
+	data193:	in	std_logic_vector((N-1) downto 0);
+	data194:	in	std_logic_vector((N-1) downto 0);
+	data195:	in	std_logic_vector((N-1) downto 0);
+	data196:	in	std_logic_vector((N-1) downto 0);
+	data197:	in	std_logic_vector((N-1) downto 0);
+	data198:	in	std_logic_vector((N-1) downto 0);
+	data199:	in	std_logic_vector((N-1) downto 0);
+	data200:	in	std_logic_vector((N-1) downto 0);
+	data201:	in	std_logic_vector((N-1) downto 0);
+	data202:	in	std_logic_vector((N-1) downto 0);
+	data203:	in	std_logic_vector((N-1) downto 0);
+	data204:	in	std_logic_vector((N-1) downto 0);
+	data205:	in	std_logic_vector((N-1) downto 0);
+	data206:	in	std_logic_vector((N-1) downto 0);
+	data207:	in	std_logic_vector((N-1) downto 0);
+	data208:	in	std_logic_vector((N-1) downto 0);
+	data209:	in	std_logic_vector((N-1) downto 0);
+	data210:	in	std_logic_vector((N-1) downto 0);
+	data211:	in	std_logic_vector((N-1) downto 0);
+	data212:	in	std_logic_vector((N-1) downto 0);
+	data213:	in	std_logic_vector((N-1) downto 0);
+	data214:	in	std_logic_vector((N-1) downto 0);
+	data215:	in	std_logic_vector((N-1) downto 0);
+	data216:	in	std_logic_vector((N-1) downto 0);
+	data217:	in	std_logic_vector((N-1) downto 0);
+	data218:	in	std_logic_vector((N-1) downto 0);
+	data219:	in	std_logic_vector((N-1) downto 0);
+	data220:	in	std_logic_vector((N-1) downto 0);
+	data221:	in	std_logic_vector((N-1) downto 0);
+	data222:	in	std_logic_vector((N-1) downto 0);
+	data223:	in	std_logic_vector((N-1) downto 0);
+	data224:	in	std_logic_vector((N-1) downto 0);
+	data225:	in	std_logic_vector((N-1) downto 0);
+	data226:	in	std_logic_vector((N-1) downto 0);
+	data227:	in	std_logic_vector((N-1) downto 0);
+	data228:	in	std_logic_vector((N-1) downto 0);
+	data229:	in	std_logic_vector((N-1) downto 0);
+	data230:	in	std_logic_vector((N-1) downto 0);
+	data231:	in	std_logic_vector((N-1) downto 0);
+	data232:	in	std_logic_vector((N-1) downto 0);
+	data233:	in	std_logic_vector((N-1) downto 0);
+	data234:	in	std_logic_vector((N-1) downto 0);
+	data235:	in	std_logic_vector((N-1) downto 0);
+	data236:	in	std_logic_vector((N-1) downto 0);
+	data237:	in	std_logic_vector((N-1) downto 0);
+	data238:	in	std_logic_vector((N-1) downto 0);
+	data239:	in	std_logic_vector((N-1) downto 0);
+	data240:	in	std_logic_vector((N-1) downto 0);
+	data241:	in	std_logic_vector((N-1) downto 0);
+	data242:	in	std_logic_vector((N-1) downto 0);
+	data243:	in	std_logic_vector((N-1) downto 0);
+	data244:	in	std_logic_vector((N-1) downto 0);
+	data245:	in	std_logic_vector((N-1) downto 0);
+	data246:	in	std_logic_vector((N-1) downto 0);
+	data247:	in	std_logic_vector((N-1) downto 0);
+	data248:	in	std_logic_vector((N-1) downto 0);
+	data249:	in	std_logic_vector((N-1) downto 0);
+	data250:	in	std_logic_vector((N-1) downto 0);
+	data251:	in	std_logic_vector((N-1) downto 0);
+	data252:	in	std_logic_vector((N-1) downto 0);
+	data253:	in	std_logic_vector((N-1) downto 0);
+	data254:	in	std_logic_vector((N-1) downto 0);
+	data255:	in	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic_vector((N-1) downto 0)
+);
+end;
+
+architecture struct_encoder256xN of encoder256xN is
+component encoder256x1 is
+port(
+	data0:		in	std_logic;
+	data1:		in	std_logic;
+	data2:		in	std_logic;
+	data3:		in	std_logic;
+	data4:		in	std_logic;
+	data5:		in	std_logic;
+	data6:		in	std_logic;
+	data7:		in	std_logic;
+	data8:		in	std_logic;
+	data9:		in	std_logic;
+	data10:		in	std_logic;
+	data11:		in	std_logic;
+	data12:		in	std_logic;
+	data13:		in	std_logic;
+	data14:		in	std_logic;
+	data15:		in	std_logic;
+	data16:		in	std_logic;
+	data17:		in	std_logic;
+	data18:		in	std_logic;
+	data19:		in	std_logic;
+	data20:		in	std_logic;
+	data21:		in	std_logic;
+	data22:		in	std_logic;
+	data23:		in	std_logic;
+	data24:		in	std_logic;
+	data25:		in	std_logic;
+	data26:		in	std_logic;
+	data27:		in	std_logic;
+	data28:		in	std_logic;
+	data29:		in	std_logic;
+	data30:		in	std_logic;
+	data31:		in	std_logic;
+	data32:		in	std_logic;
+	data33:		in	std_logic;
+	data34:		in	std_logic;
+	data35:		in	std_logic;
+	data36:		in	std_logic;
+	data37:		in	std_logic;
+	data38:		in	std_logic;
+	data39:		in	std_logic;
+	data40:		in	std_logic;
+	data41:		in	std_logic;
+	data42:		in	std_logic;
+	data43:		in	std_logic;
+	data44:		in	std_logic;
+	data45:		in	std_logic;
+	data46:		in	std_logic;
+	data47:		in	std_logic;
+	data48:		in	std_logic;
+	data49:		in	std_logic;
+	data50:		in	std_logic;
+	data51:		in	std_logic;
+	data52:		in	std_logic;
+	data53:		in	std_logic;
+	data54:		in	std_logic;
+	data55:		in	std_logic;
+	data56:		in	std_logic;
+	data57:		in	std_logic;
+	data58:		in	std_logic;
+	data59:		in	std_logic;
+	data60:		in	std_logic;
+	data61:		in	std_logic;
+	data62:		in	std_logic;
+	data63:		in	std_logic;
+	data64:		in	std_logic;
+	data65:		in	std_logic;
+	data66:		in	std_logic;
+	data67:		in	std_logic;
+	data68:		in	std_logic;
+	data69:		in	std_logic;
+	data70:		in	std_logic;
+	data71:		in	std_logic;
+	data72:		in	std_logic;
+	data73:		in	std_logic;
+	data74:		in	std_logic;
+	data75:		in	std_logic;
+	data76:		in	std_logic;
+	data77:		in	std_logic;
+	data78:		in	std_logic;
+	data79:		in	std_logic;
+	data80:		in	std_logic;
+	data81:		in	std_logic;
+	data82:		in	std_logic;
+	data83:		in	std_logic;
+	data84:		in	std_logic;
+	data85:		in	std_logic;
+	data86:		in	std_logic;
+	data87:		in	std_logic;
+	data88:		in	std_logic;
+	data89:		in	std_logic;
+	data90:		in	std_logic;
+	data91:		in	std_logic;
+	data92:		in	std_logic;
+	data93:		in	std_logic;
+	data94:		in	std_logic;
+	data95:		in	std_logic;
+	data96:		in	std_logic;
+	data97:		in	std_logic;
+	data98:		in	std_logic;
+	data99:		in	std_logic;
+	data100:	in	std_logic;
+	data101:	in	std_logic;
+	data102:	in	std_logic;
+	data103:	in	std_logic;
+	data104:	in	std_logic;
+	data105:	in	std_logic;
+	data106:	in	std_logic;
+	data107:	in	std_logic;
+	data108:	in	std_logic;
+	data109:	in	std_logic;
+	data110:	in	std_logic;
+	data111:	in	std_logic;
+	data112:	in	std_logic;
+	data113:	in	std_logic;
+	data114:	in	std_logic;
+	data115:	in	std_logic;
+	data116:	in	std_logic;
+	data117:	in	std_logic;
+	data118:	in	std_logic;
+	data119:	in	std_logic;
+	data120:	in	std_logic;
+	data121:	in	std_logic;
+	data122:	in	std_logic;
+	data123:	in	std_logic;
+	data124:	in	std_logic;
+	data125:	in	std_logic;
+	data126:	in	std_logic;
+	data127:	in	std_logic;
+	data128:	in	std_logic;
+	data129:	in	std_logic;
+	data130:	in	std_logic;
+	data131:	in	std_logic;
+	data132:	in	std_logic;
+	data133:	in	std_logic;
+	data134:	in	std_logic;
+	data135:	in	std_logic;
+	data136:	in	std_logic;
+	data137:	in	std_logic;
+	data138:	in	std_logic;
+	data139:	in	std_logic;
+	data140:	in	std_logic;
+	data141:	in	std_logic;
+	data142:	in	std_logic;
+	data143:	in	std_logic;
+	data144:	in	std_logic;
+	data145:	in	std_logic;
+	data146:	in	std_logic;
+	data147:	in	std_logic;
+	data148:	in	std_logic;
+	data149:	in	std_logic;
+	data150:	in	std_logic;
+	data151:	in	std_logic;
+	data152:	in	std_logic;
+	data153:	in	std_logic;
+	data154:	in	std_logic;
+	data155:	in	std_logic;
+	data156:	in	std_logic;
+	data157:	in	std_logic;
+	data158:	in	std_logic;
+	data159:	in	std_logic;
+	data160:	in	std_logic;
+	data161:	in	std_logic;
+	data162:	in	std_logic;
+	data163:	in	std_logic;
+	data164:	in	std_logic;
+	data165:	in	std_logic;
+	data166:	in	std_logic;
+	data167:	in	std_logic;
+	data168:	in	std_logic;
+	data169:	in	std_logic;
+	data170:	in	std_logic;
+	data171:	in	std_logic;
+	data172:	in	std_logic;
+	data173:	in	std_logic;
+	data174:	in	std_logic;
+	data175:	in	std_logic;
+	data176:	in	std_logic;
+	data177:	in	std_logic;
+	data178:	in	std_logic;
+	data179:	in	std_logic;
+	data180:	in	std_logic;
+	data181:	in	std_logic;
+	data182:	in	std_logic;
+	data183:	in	std_logic;
+	data184:	in	std_logic;
+	data185:	in	std_logic;
+	data186:	in	std_logic;
+	data187:	in	std_logic;
+	data188:	in	std_logic;
+	data189:	in	std_logic;
+	data190:	in	std_logic;
+	data191:	in	std_logic;
+	data192:	in	std_logic;
+	data193:	in	std_logic;
+	data194:	in	std_logic;
+	data195:	in	std_logic;
+	data196:	in	std_logic;
+	data197:	in	std_logic;
+	data198:	in	std_logic;
+	data199:	in	std_logic;
+	data200:	in	std_logic;
+	data201:	in	std_logic;
+	data202:	in	std_logic;
+	data203:	in	std_logic;
+	data204:	in	std_logic;
+	data205:	in	std_logic;
+	data206:	in	std_logic;
+	data207:	in	std_logic;
+	data208:	in	std_logic;
+	data209:	in	std_logic;
+	data210:	in	std_logic;
+	data211:	in	std_logic;
+	data212:	in	std_logic;
+	data213:	in	std_logic;
+	data214:	in	std_logic;
+	data215:	in	std_logic;
+	data216:	in	std_logic;
+	data217:	in	std_logic;
+	data218:	in	std_logic;
+	data219:	in	std_logic;
+	data220:	in	std_logic;
+	data221:	in	std_logic;
+	data222:	in	std_logic;
+	data223:	in	std_logic;
+	data224:	in	std_logic;
+	data225:	in	std_logic;
+	data226:	in	std_logic;
+	data227:	in	std_logic;
+	data228:	in	std_logic;
+	data229:	in	std_logic;
+	data230:	in	std_logic;
+	data231:	in	std_logic;
+	data232:	in	std_logic;
+	data233:	in	std_logic;
+	data234:	in	std_logic;
+	data235:	in	std_logic;
+	data236:	in	std_logic;
+	data237:	in	std_logic;
+	data238:	in	std_logic;
+	data239:	in	std_logic;
+	data240:	in	std_logic;
+	data241:	in	std_logic;
+	data242:	in	std_logic;
+	data243:	in	std_logic;
+	data244:	in	std_logic;
+	data245:	in	std_logic;
+	data246:	in	std_logic;
+	data247:	in	std_logic;
+	data248:	in	std_logic;
+	data249:	in	std_logic;
+	data250:	in	std_logic;
+	data251:	in	std_logic;
+	data252:	in	std_logic;
+	data253:	in	std_logic;
+	data254:	in	std_logic;
+	data255:	in	std_logic;
+	address:	in	std_logic_vector(7 downto 0);
+	output:		out	std_logic
+);
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u: encoder256x1 port map(
+			data0		=> data0(i),
+			data1		=> data1(i),
+			data2		=> data2(i),
+			data3		=> data3(i),
+			data4		=> data4(i),
+			data5		=> data5(i),
+			data6		=> data6(i),
+			data7		=> data7(i),
+			data8		=> data8(i),
+			data9		=> data9(i),
+			data10		=> data10(i),
+			data11		=> data11(i),
+			data12		=> data12(i),
+			data13		=> data13(i),
+			data14		=> data14(i),
+			data15		=> data15(i),
+			data16		=> data16(i),
+			data17		=> data17(i),
+			data18		=> data18(i),
+			data19		=> data19(i),
+			data20		=> data20(i),
+			data21		=> data21(i),
+			data22		=> data22(i),
+			data23		=> data23(i),
+			data24		=> data24(i),
+			data25		=> data25(i),
+			data26		=> data26(i),
+			data27		=> data27(i),
+			data28		=> data28(i),
+			data29		=> data29(i),
+			data30		=> data30(i),
+			data31		=> data31(i),
+			data32		=> data32(i),
+			data33		=> data33(i),
+			data34		=> data34(i),
+			data35		=> data35(i),
+			data36		=> data36(i),
+			data37		=> data37(i),
+			data38		=> data38(i),
+			data39		=> data39(i),
+			data40		=> data40(i),
+			data41		=> data41(i),
+			data42		=> data42(i),
+			data43		=> data43(i),
+			data44		=> data44(i),
+			data45		=> data45(i),
+			data46		=> data46(i),
+			data47		=> data47(i),
+			data48		=> data48(i),
+			data49		=> data49(i),
+			data50		=> data50(i),
+			data51		=> data51(i),
+			data52		=> data52(i),
+			data53		=> data53(i),
+			data54		=> data54(i),
+			data55		=> data55(i),
+			data56		=> data56(i),
+			data57		=> data57(i),
+			data58		=> data58(i),
+			data59		=> data59(i),
+			data60		=> data60(i),
+			data61		=> data61(i),
+			data62		=> data62(i),
+			data63		=> data63(i),
+			data64		=> data64(i),
+			data65		=> data65(i),
+			data66		=> data66(i),
+			data67		=> data67(i),
+			data68		=> data68(i),
+			data69		=> data69(i),
+			data70		=> data70(i),
+			data71		=> data71(i),
+			data72		=> data72(i),
+			data73		=> data73(i),
+			data74		=> data74(i),
+			data75		=> data75(i),
+			data76		=> data76(i),
+			data77		=> data77(i),
+			data78		=> data78(i),
+			data79		=> data79(i),
+			data80		=> data80(i),
+			data81		=> data81(i),
+			data82		=> data82(i),
+			data83		=> data83(i),
+			data84		=> data84(i),
+			data85		=> data85(i),
+			data86		=> data86(i),
+			data87		=> data87(i),
+			data88		=> data88(i),
+			data89		=> data89(i),
+			data90		=> data90(i),
+			data91		=> data91(i),
+			data92		=> data92(i),
+			data93		=> data93(i),
+			data94		=> data94(i),
+			data95		=> data95(i),
+			data96		=> data96(i),
+			data97		=> data97(i),
+			data98		=> data98(i),
+			data99		=> data99(i),
+			data100		=> data100(i),
+			data101		=> data101(i),
+			data102		=> data102(i),
+			data103		=> data103(i),
+			data104		=> data104(i),
+			data105		=> data105(i),
+			data106		=> data106(i),
+			data107		=> data107(i),
+			data108		=> data108(i),
+			data109		=> data109(i),
+			data110		=> data110(i),
+			data111		=> data111(i),
+			data112		=> data112(i),
+			data113		=> data113(i),
+			data114		=> data114(i),
+			data115		=> data115(i),
+			data116		=> data116(i),
+			data117		=> data117(i),
+			data118		=> data118(i),
+			data119		=> data119(i),
+			data120		=> data120(i),
+			data121		=> data121(i),
+			data122		=> data122(i),
+			data123		=> data123(i),
+			data124		=> data124(i),
+			data125		=> data125(i),
+			data126		=> data126(i),
+			data127		=> data127(i),
+			data128		=> data128(i),
+			data129		=> data129(i),
+			data130		=> data130(i),
+			data131		=> data131(i),
+			data132		=> data132(i),
+			data133		=> data133(i),
+			data134		=> data134(i),
+			data135		=> data135(i),
+			data136		=> data136(i),
+			data137		=> data137(i),
+			data138		=> data138(i),
+			data139		=> data139(i),
+			data140		=> data140(i),
+			data141		=> data141(i),
+			data142		=> data142(i),
+			data143		=> data143(i),
+			data144		=> data144(i),
+			data145		=> data145(i),
+			data146		=> data146(i),
+			data147		=> data147(i),
+			data148		=> data148(i),
+			data149		=> data149(i),
+			data150		=> data150(i),
+			data151		=> data151(i),
+			data152		=> data152(i),
+			data153		=> data153(i),
+			data154		=> data154(i),
+			data155		=> data155(i),
+			data156		=> data156(i),
+			data157		=> data157(i),
+			data158		=> data158(i),
+			data159		=> data159(i),
+			data160		=> data160(i),
+			data161		=> data161(i),
+			data162		=> data162(i),
+			data163		=> data163(i),
+			data164		=> data164(i),
+			data165		=> data165(i),
+			data166		=> data166(i),
+			data167		=> data167(i),
+			data168		=> data168(i),
+			data169		=> data169(i),
+			data170		=> data170(i),
+			data171		=> data171(i),
+			data172		=> data172(i),
+			data173		=> data173(i),
+			data174		=> data174(i),
+			data175		=> data175(i),
+			data176		=> data176(i),
+			data177		=> data177(i),
+			data178		=> data178(i),
+			data179		=> data179(i),
+			data180		=> data180(i),
+			data181		=> data181(i),
+			data182		=> data182(i),
+			data183		=> data183(i),
+			data184		=> data184(i),
+			data185		=> data185(i),
+			data186		=> data186(i),
+			data187		=> data187(i),
+			data188		=> data188(i),
+			data189		=> data189(i),
+			data190		=> data190(i),
+			data191		=> data191(i),
+			data192		=> data192(i),
+			data193		=> data193(i),
+			data194		=> data194(i),
+			data195		=> data195(i),
+			data196		=> data196(i),
+			data197		=> data197(i),
+			data198		=> data198(i),
+			data199		=> data199(i),
+			data200		=> data200(i),
+			data201		=> data201(i),
+			data202		=> data202(i),
+			data203		=> data203(i),
+			data204		=> data204(i),
+			data205		=> data205(i),
+			data206		=> data206(i),
+			data207		=> data207(i),
+			data208		=> data208(i),
+			data209		=> data209(i),
+			data210		=> data210(i),
+			data211		=> data211(i),
+			data212		=> data212(i),
+			data213		=> data213(i),
+			data214		=> data214(i),
+			data215		=> data215(i),
+			data216		=> data216(i),
+			data217		=> data217(i),
+			data218		=> data218(i),
+			data219		=> data219(i),
+			data220		=> data220(i),
+			data221		=> data221(i),
+			data222		=> data222(i),
+			data223		=> data223(i),
+			data224		=> data224(i),
+			data225		=> data225(i),
+			data226		=> data226(i),
+			data227		=> data227(i),
+			data228		=> data228(i),
+			data229		=> data229(i),
+			data230		=> data230(i),
+			data231		=> data231(i),
+			data232		=> data232(i),
+			data233		=> data233(i),
+			data234		=> data234(i),
+			data235		=> data235(i),
+			data236		=> data236(i),
+			data237		=> data237(i),
+			data238		=> data238(i),
+			data239		=> data239(i),
+			data240		=> data240(i),
+			data241		=> data241(i),
+			data242		=> data242(i),
+			data243		=> data243(i),
+			data244		=> data244(i),
+			data245		=> data245(i),
+			data246		=> data246(i),
+			data247		=> data247(i),
+			data248		=> data248(i),
+			data249		=> data249(i),
+			data250		=> data250(i),
+			data251		=> data251(i),
+			data252		=> data252(i),
+			data253		=> data253(i),
+			data254		=> data254(i),
+			data255		=> data255(i),
+			address		=> address,
+			output		=> output(i)
+		);
+	end generate u1;
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity decoder1x256 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	y16:		out	std_logic;
+	y17:		out	std_logic;
+	y18:		out	std_logic;
+	y19:		out	std_logic;
+	y20:		out	std_logic;
+	y21:		out	std_logic;
+	y22:		out	std_logic;
+	y23:		out	std_logic;
+	y24:		out	std_logic;
+	y25:		out	std_logic;
+	y26:		out	std_logic;
+	y27:		out	std_logic;
+	y28:		out	std_logic;
+	y29:		out	std_logic;
+	y30:		out	std_logic;
+	y31:		out	std_logic;
+	y32:		out	std_logic;
+	y33:		out	std_logic;
+	y34:		out	std_logic;
+	y35:		out	std_logic;
+	y36:		out	std_logic;
+	y37:		out	std_logic;
+	y38:		out	std_logic;
+	y39:		out	std_logic;
+	y40:		out	std_logic;
+	y41:		out	std_logic;
+	y42:		out	std_logic;
+	y43:		out	std_logic;
+	y44:		out	std_logic;
+	y45:		out	std_logic;
+	y46:		out	std_logic;
+	y47:		out	std_logic;
+	y48:		out	std_logic;
+	y49:		out	std_logic;
+	y50:		out	std_logic;
+	y51:		out	std_logic;
+	y52:		out	std_logic;
+	y53:		out	std_logic;
+	y54:		out	std_logic;
+	y55:		out	std_logic;
+	y56:		out	std_logic;
+	y57:		out	std_logic;
+	y58:		out	std_logic;
+	y59:		out	std_logic;
+	y60:		out	std_logic;
+	y61:		out	std_logic;
+	y62:		out	std_logic;
+	y63:		out	std_logic;
+	y64:		out	std_logic;
+	y65:		out	std_logic;
+	y66:		out	std_logic;
+	y67:		out	std_logic;
+	y68:		out	std_logic;
+	y69:		out	std_logic;
+	y70:		out	std_logic;
+	y71:		out	std_logic;
+	y72:		out	std_logic;
+	y73:		out	std_logic;
+	y74:		out	std_logic;
+	y75:		out	std_logic;
+	y76:		out	std_logic;
+	y77:		out	std_logic;
+	y78:		out	std_logic;
+	y79:		out	std_logic;
+	y80:		out	std_logic;
+	y81:		out	std_logic;
+	y82:		out	std_logic;
+	y83:		out	std_logic;
+	y84:		out	std_logic;
+	y85:		out	std_logic;
+	y86:		out	std_logic;
+	y87:		out	std_logic;
+	y88:		out	std_logic;
+	y89:		out	std_logic;
+	y90:		out	std_logic;
+	y91:		out	std_logic;
+	y92:		out	std_logic;
+	y93:		out	std_logic;
+	y94:		out	std_logic;
+	y95:		out	std_logic;
+	y96:		out	std_logic;
+	y97:		out	std_logic;
+	y98:		out	std_logic;
+	y99:		out	std_logic;
+	y100:		out	std_logic;
+	y101:		out	std_logic;
+	y102:		out	std_logic;
+	y103:		out	std_logic;
+	y104:		out	std_logic;
+	y105:		out	std_logic;
+	y106:		out	std_logic;
+	y107:		out	std_logic;
+	y108:		out	std_logic;
+	y109:		out	std_logic;
+	y110:		out	std_logic;
+	y111:		out	std_logic;
+	y112:		out	std_logic;
+	y113:		out	std_logic;
+	y114:		out	std_logic;
+	y115:		out	std_logic;
+	y116:		out	std_logic;
+	y117:		out	std_logic;
+	y118:		out	std_logic;
+	y119:		out	std_logic;
+	y120:		out	std_logic;
+	y121:		out	std_logic;
+	y122:		out	std_logic;
+	y123:		out	std_logic;
+	y124:		out	std_logic;
+	y125:		out	std_logic;
+	y126:		out	std_logic;
+	y127:		out	std_logic;
+	y128:		out	std_logic;
+	y129:		out	std_logic;
+	y130:		out	std_logic;
+	y131:		out	std_logic;
+	y132:		out	std_logic;
+	y133:		out	std_logic;
+	y134:		out	std_logic;
+	y135:		out	std_logic;
+	y136:		out	std_logic;
+	y137:		out	std_logic;
+	y138:		out	std_logic;
+	y139:		out	std_logic;
+	y140:		out	std_logic;
+	y141:		out	std_logic;
+	y142:		out	std_logic;
+	y143:		out	std_logic;
+	y144:		out	std_logic;
+	y145:		out	std_logic;
+	y146:		out	std_logic;
+	y147:		out	std_logic;
+	y148:		out	std_logic;
+	y149:		out	std_logic;
+	y150:		out	std_logic;
+	y151:		out	std_logic;
+	y152:		out	std_logic;
+	y153:		out	std_logic;
+	y154:		out	std_logic;
+	y155:		out	std_logic;
+	y156:		out	std_logic;
+	y157:		out	std_logic;
+	y158:		out	std_logic;
+	y159:		out	std_logic;
+	y160:		out	std_logic;
+	y161:		out	std_logic;
+	y162:		out	std_logic;
+	y163:		out	std_logic;
+	y164:		out	std_logic;
+	y165:		out	std_logic;
+	y166:		out	std_logic;
+	y167:		out	std_logic;
+	y168:		out	std_logic;
+	y169:		out	std_logic;
+	y170:		out	std_logic;
+	y171:		out	std_logic;
+	y172:		out	std_logic;
+	y173:		out	std_logic;
+	y174:		out	std_logic;
+	y175:		out	std_logic;
+	y176:		out	std_logic;
+	y177:		out	std_logic;
+	y178:		out	std_logic;
+	y179:		out	std_logic;
+	y180:		out	std_logic;
+	y181:		out	std_logic;
+	y182:		out	std_logic;
+	y183:		out	std_logic;
+	y184:		out	std_logic;
+	y185:		out	std_logic;
+	y186:		out	std_logic;
+	y187:		out	std_logic;
+	y188:		out	std_logic;
+	y189:		out	std_logic;
+	y190:		out	std_logic;
+	y191:		out	std_logic;
+	y192:		out	std_logic;
+	y193:		out	std_logic;
+	y194:		out	std_logic;
+	y195:		out	std_logic;
+	y196:		out	std_logic;
+	y197:		out	std_logic;
+	y198:		out	std_logic;
+	y199:		out	std_logic;
+	y200:		out	std_logic;
+	y201:		out	std_logic;
+	y202:		out	std_logic;
+	y203:		out	std_logic;
+	y204:		out	std_logic;
+	y205:		out	std_logic;
+	y206:		out	std_logic;
+	y207:		out	std_logic;
+	y208:		out	std_logic;
+	y209:		out	std_logic;
+	y210:		out	std_logic;
+	y211:		out	std_logic;
+	y212:		out	std_logic;
+	y213:		out	std_logic;
+	y214:		out	std_logic;
+	y215:		out	std_logic;
+	y216:		out	std_logic;
+	y217:		out	std_logic;
+	y218:		out	std_logic;
+	y219:		out	std_logic;
+	y220:		out	std_logic;
+	y221:		out	std_logic;
+	y222:		out	std_logic;
+	y223:		out	std_logic;
+	y224:		out	std_logic;
+	y225:		out	std_logic;
+	y226:		out	std_logic;
+	y227:		out	std_logic;
+	y228:		out	std_logic;
+	y229:		out	std_logic;
+	y230:		out	std_logic;
+	y231:		out	std_logic;
+	y232:		out	std_logic;
+	y233:		out	std_logic;
+	y234:		out	std_logic;
+	y235:		out	std_logic;
+	y236:		out	std_logic;
+	y237:		out	std_logic;
+	y238:		out	std_logic;
+	y239:		out	std_logic;
+	y240:		out	std_logic;
+	y241:		out	std_logic;
+	y242:		out	std_logic;
+	y243:		out	std_logic;
+	y244:		out	std_logic;
+	y245:		out	std_logic;
+	y246:		out	std_logic;
+	y247:		out	std_logic;
+	y248:		out	std_logic;
+	y249:		out	std_logic;
+	y250:		out	std_logic;
+	y251:		out	std_logic;
+	y252:		out	std_logic;
+	y253:		out	std_logic;
+	y254:		out	std_logic;
+	y255:		out	std_logic;
+	address:	in	std_logic_vector(7 downto 0)
+);
+end;
+
+architecture struct_decoder1x256 of decoder1x256 is
+begin
+	y0		<= data when address = "00000000" else '0';
+	y1		<= data when address = "00000001" else '0';
+	y2		<= data when address = "00000010" else '0';
+	y3		<= data when address = "00000011" else '0';
+	y4		<= data when address = "00000100" else '0';
+	y5		<= data when address = "00000101" else '0';
+	y6		<= data when address = "00000110" else '0';
+	y7		<= data when address = "00000111" else '0';
+	y8		<= data when address = "00001000" else '0';
+	y9		<= data when address = "00001001" else '0';
+	y10		<= data when address = "00001010" else '0';
+	y11		<= data when address = "00001011" else '0';
+	y12		<= data when address = "00001100" else '0';
+	y13		<= data when address = "00001101" else '0';
+	y14		<= data when address = "00001110" else '0';
+	y15		<= data when address = "00001111" else '0';
+	y16		<= data when address = "00010000" else '0';
+	y17		<= data when address = "00010001" else '0';
+	y18		<= data when address = "00010010" else '0';
+	y19		<= data when address = "00010011" else '0';
+	y20		<= data when address = "00010100" else '0';
+	y21		<= data when address = "00010101" else '0';
+	y22		<= data when address = "00010110" else '0';
+	y23		<= data when address = "00010111" else '0';
+	y24		<= data when address = "00011000" else '0';
+	y25		<= data when address = "00011001" else '0';
+	y26		<= data when address = "00011010" else '0';
+	y27		<= data when address = "00011011" else '0';
+	y28		<= data when address = "00011100" else '0';
+	y29		<= data when address = "00011101" else '0';
+	y30		<= data when address = "00011110" else '0';
+	y31		<= data when address = "00011111" else '0';
+	y32		<= data when address = "00100000" else '0';
+	y33		<= data when address = "00100001" else '0';
+	y34		<= data when address = "00100010" else '0';
+	y35		<= data when address = "00100011" else '0';
+	y36		<= data when address = "00100100" else '0';
+	y37		<= data when address = "00100101" else '0';
+	y38		<= data when address = "00100110" else '0';
+	y39		<= data when address = "00100111" else '0';
+	y40		<= data when address = "00101000" else '0';
+	y41		<= data when address = "00101001" else '0';
+	y42		<= data when address = "00101010" else '0';
+	y43		<= data when address = "00101011" else '0';
+	y44		<= data when address = "00101100" else '0';
+	y45		<= data when address = "00101101" else '0';
+	y46		<= data when address = "00101110" else '0';
+	y47		<= data when address = "00101111" else '0';
+	y48		<= data when address = "00110000" else '0';
+	y49		<= data when address = "00110001" else '0';
+	y50		<= data when address = "00110010" else '0';
+	y51		<= data when address = "00110011" else '0';
+	y52		<= data when address = "00110100" else '0';
+	y53		<= data when address = "00110101" else '0';
+	y54		<= data when address = "00110110" else '0';
+	y55		<= data when address = "00110111" else '0';
+	y56		<= data when address = "00111000" else '0';
+	y57		<= data when address = "00111001" else '0';
+	y58		<= data when address = "00111010" else '0';
+	y59		<= data when address = "00111011" else '0';
+	y60		<= data when address = "00111100" else '0';
+	y61		<= data when address = "00111101" else '0';
+	y62		<= data when address = "00111110" else '0';
+	y63		<= data when address = "00111111" else '0';
+	y64		<= data when address = "01000000" else '0';
+	y65		<= data when address = "01000001" else '0';
+	y66		<= data when address = "01000010" else '0';
+	y67		<= data when address = "01000011" else '0';
+	y68		<= data when address = "01000100" else '0';
+	y69		<= data when address = "01000101" else '0';
+	y70		<= data when address = "01000110" else '0';
+	y71		<= data when address = "01000111" else '0';
+	y72		<= data when address = "01001000" else '0';
+	y73		<= data when address = "01001001" else '0';
+	y74		<= data when address = "01001010" else '0';
+	y75		<= data when address = "01001011" else '0';
+	y76		<= data when address = "01001100" else '0';
+	y77		<= data when address = "01001101" else '0';
+	y78		<= data when address = "01001110" else '0';
+	y79		<= data when address = "01001111" else '0';
+	y80		<= data when address = "01010000" else '0';
+	y81		<= data when address = "01010001" else '0';
+	y82		<= data when address = "01010010" else '0';
+	y83		<= data when address = "01010011" else '0';
+	y84		<= data when address = "01010100" else '0';
+	y85		<= data when address = "01010101" else '0';
+	y86		<= data when address = "01010110" else '0';
+	y87		<= data when address = "01010111" else '0';
+	y88		<= data when address = "01011000" else '0';
+	y89		<= data when address = "01011001" else '0';
+	y90		<= data when address = "01011010" else '0';
+	y91		<= data when address = "01011011" else '0';
+	y92		<= data when address = "01011100" else '0';
+	y93		<= data when address = "01011101" else '0';
+	y94		<= data when address = "01011110" else '0';
+	y95		<= data when address = "01011111" else '0';
+	y96		<= data when address = "01100000" else '0';
+	y97		<= data when address = "01100001" else '0';
+	y98		<= data when address = "01100010" else '0';
+	y99		<= data when address = "01100011" else '0';
+	y100	<= data when address = "01100100" else '0';
+	y101	<= data when address = "01100101" else '0';
+	y102	<= data when address = "01100110" else '0';
+	y103	<= data when address = "01100111" else '0';
+	y104	<= data when address = "01101000" else '0';
+	y105	<= data when address = "01101001" else '0';
+	y106	<= data when address = "01101010" else '0';
+	y107	<= data when address = "01101011" else '0';
+	y108	<= data when address = "01101100" else '0';
+	y109	<= data when address = "01101101" else '0';
+	y110	<= data when address = "01101110" else '0';
+	y111	<= data when address = "01101111" else '0';
+	y112	<= data when address = "01110000" else '0';
+	y113	<= data when address = "01110001" else '0';
+	y114	<= data when address = "01110010" else '0';
+	y115	<= data when address = "01110011" else '0';
+	y116	<= data when address = "01110100" else '0';
+	y117	<= data when address = "01110101" else '0';
+	y118	<= data when address = "01110110" else '0';
+	y119	<= data when address = "01110111" else '0';
+	y120	<= data when address = "01111000" else '0';
+	y121	<= data when address = "01111001" else '0';
+	y122	<= data when address = "01111010" else '0';
+	y123	<= data when address = "01111011" else '0';
+	y124	<= data when address = "01111100" else '0';
+	y125	<= data when address = "01111101" else '0';
+	y126	<= data when address = "01111110" else '0';
+	y127	<= data when address = "01111111" else '0';
+	y128	<= data when address = "10000000" else '0';
+	y129	<= data when address = "10000001" else '0';
+	y130	<= data when address = "10000010" else '0';
+	y131	<= data when address = "10000011" else '0';
+	y132	<= data when address = "10000100" else '0';
+	y133	<= data when address = "10000101" else '0';
+	y134	<= data when address = "10000110" else '0';
+	y135	<= data when address = "10000111" else '0';
+	y136	<= data when address = "10001000" else '0';
+	y137	<= data when address = "10001001" else '0';
+	y138	<= data when address = "10001010" else '0';
+	y139	<= data when address = "10001011" else '0';
+	y140	<= data when address = "10001100" else '0';
+	y141	<= data when address = "10001101" else '0';
+	y142	<= data when address = "10001110" else '0';
+	y143	<= data when address = "10001111" else '0';
+	y144	<= data when address = "10010000" else '0';
+	y145	<= data when address = "10010001" else '0';
+	y146	<= data when address = "10010010" else '0';
+	y147	<= data when address = "10010011" else '0';
+	y148	<= data when address = "10010100" else '0';
+	y149	<= data when address = "10010101" else '0';
+	y150	<= data when address = "10010110" else '0';
+	y151	<= data when address = "10010111" else '0';
+	y152	<= data when address = "10011000" else '0';
+	y153	<= data when address = "10011001" else '0';
+	y154	<= data when address = "10011010" else '0';
+	y155	<= data when address = "10011011" else '0';
+	y156	<= data when address = "10011100" else '0';
+	y157	<= data when address = "10011101" else '0';
+	y158	<= data when address = "10011110" else '0';
+	y159	<= data when address = "10011111" else '0';
+	y160	<= data when address = "10100000" else '0';
+	y161	<= data when address = "10100001" else '0';
+	y162	<= data when address = "10100010" else '0';
+	y163	<= data when address = "10100011" else '0';
+	y164	<= data when address = "10100100" else '0';
+	y165	<= data when address = "10100101" else '0';
+	y166	<= data when address = "10100110" else '0';
+	y167	<= data when address = "10100111" else '0';
+	y168	<= data when address = "10101000" else '0';
+	y169	<= data when address = "10101001" else '0';
+	y170	<= data when address = "10101010" else '0';
+	y171	<= data when address = "10101011" else '0';
+	y172	<= data when address = "10101100" else '0';
+	y173	<= data when address = "10101101" else '0';
+	y174	<= data when address = "10101110" else '0';
+	y175	<= data when address = "10101111" else '0';
+	y176	<= data when address = "10110000" else '0';
+	y177	<= data when address = "10110001" else '0';
+	y178	<= data when address = "10110010" else '0';
+	y179	<= data when address = "10110011" else '0';
+	y180	<= data when address = "10110100" else '0';
+	y181	<= data when address = "10110101" else '0';
+	y182	<= data when address = "10110110" else '0';
+	y183	<= data when address = "10110111" else '0';
+	y184	<= data when address = "10111000" else '0';
+	y185	<= data when address = "10111001" else '0';
+	y186	<= data when address = "10111010" else '0';
+	y187	<= data when address = "10111011" else '0';
+	y188	<= data when address = "10111100" else '0';
+	y189	<= data when address = "10111101" else '0';
+	y190	<= data when address = "10111110" else '0';
+	y191	<= data when address = "10111111" else '0';
+	y192	<= data when address = "11000000" else '0';
+	y193	<= data when address = "11000001" else '0';
+	y194	<= data when address = "11000010" else '0';
+	y195	<= data when address = "11000011" else '0';
+	y196	<= data when address = "11000100" else '0';
+	y197	<= data when address = "11000101" else '0';
+	y198	<= data when address = "11000110" else '0';
+	y199	<= data when address = "11000111" else '0';
+	y200	<= data when address = "11001000" else '0';
+	y201	<= data when address = "11001001" else '0';
+	y202	<= data when address = "11001010" else '0';
+	y203	<= data when address = "11001011" else '0';
+	y204	<= data when address = "11001100" else '0';
+	y205	<= data when address = "11001101" else '0';
+	y206	<= data when address = "11001110" else '0';
+	y207	<= data when address = "11001111" else '0';
+	y208	<= data when address = "11010000" else '0';
+	y209	<= data when address = "11010001" else '0';
+	y210	<= data when address = "11010010" else '0';
+	y211	<= data when address = "11010011" else '0';
+	y212	<= data when address = "11010100" else '0';
+	y213	<= data when address = "11010101" else '0';
+	y214	<= data when address = "11010110" else '0';
+	y215	<= data when address = "11010111" else '0';
+	y216	<= data when address = "11011000" else '0';
+	y217	<= data when address = "11011001" else '0';
+	y218	<= data when address = "11011010" else '0';
+	y219	<= data when address = "11011011" else '0';
+	y220	<= data when address = "11011100" else '0';
+	y221	<= data when address = "11011101" else '0';
+	y222	<= data when address = "11011110" else '0';
+	y223	<= data when address = "11011111" else '0';
+	y224	<= data when address = "11100000" else '0';
+	y225	<= data when address = "11100001" else '0';
+	y226	<= data when address = "11100010" else '0';
+	y227	<= data when address = "11100011" else '0';
+	y228	<= data when address = "11100100" else '0';
+	y229	<= data when address = "11100101" else '0';
+	y230	<= data when address = "11100110" else '0';
+	y231	<= data when address = "11100111" else '0';
+	y232	<= data when address = "11101000" else '0';
+	y233	<= data when address = "11101001" else '0';
+	y234	<= data when address = "11101010" else '0';
+	y235	<= data when address = "11101011" else '0';
+	y236	<= data when address = "11101100" else '0';
+	y237	<= data when address = "11101101" else '0';
+	y238	<= data when address = "11101110" else '0';
+	y239	<= data when address = "11101111" else '0';
+	y240	<= data when address = "11110000" else '0';
+	y241	<= data when address = "11110001" else '0';
+	y242	<= data when address = "11110010" else '0';
+	y243	<= data when address = "11110011" else '0';
+	y244	<= data when address = "11110100" else '0';
+	y245	<= data when address = "11110101" else '0';
+	y246	<= data when address = "11110110" else '0';
+	y247	<= data when address = "11110111" else '0';
+	y248	<= data when address = "11111000" else '0';
+	y249	<= data when address = "11111001" else '0';
+	y250	<= data when address = "11111010" else '0';
+	y251	<= data when address = "11111011" else '0';
+	y252	<= data when address = "11111100" else '0';
+	y253	<= data when address = "11111101" else '0';
+	y254	<= data when address = "11111110" else '0';
+	y255	<= data when address = "11111111" else '0';
+end;
+
+library	ieee;
+use	ieee.std_logic_1164.all;
+
+entity decoderNx256 is
+generic(
+	N:	positive
+);
+port(
+	data:		in	std_logic_vector((N-1) downto 0);
+	y0:			out	std_logic_vector((N-1) downto 0);
+	y1:			out	std_logic_vector((N-1) downto 0);
+	y2:			out	std_logic_vector((N-1) downto 0);
+	y3:			out	std_logic_vector((N-1) downto 0);
+	y4:			out	std_logic_vector((N-1) downto 0);
+	y5:			out	std_logic_vector((N-1) downto 0);
+	y6:			out	std_logic_vector((N-1) downto 0);
+	y7:			out	std_logic_vector((N-1) downto 0);
+	y8:			out	std_logic_vector((N-1) downto 0);
+	y9:			out	std_logic_vector((N-1) downto 0);
+	y10:		out	std_logic_vector((N-1) downto 0);
+	y11:		out	std_logic_vector((N-1) downto 0);
+	y12:		out	std_logic_vector((N-1) downto 0);
+	y13:		out	std_logic_vector((N-1) downto 0);
+	y14:		out	std_logic_vector((N-1) downto 0);
+	y15:		out	std_logic_vector((N-1) downto 0);
+	y16:		out	std_logic_vector((N-1) downto 0);
+	y17:		out	std_logic_vector((N-1) downto 0);
+	y18:		out	std_logic_vector((N-1) downto 0);
+	y19:		out	std_logic_vector((N-1) downto 0);
+	y20:		out	std_logic_vector((N-1) downto 0);
+	y21:		out	std_logic_vector((N-1) downto 0);
+	y22:		out	std_logic_vector((N-1) downto 0);
+	y23:		out	std_logic_vector((N-1) downto 0);
+	y24:		out	std_logic_vector((N-1) downto 0);
+	y25:		out	std_logic_vector((N-1) downto 0);
+	y26:		out	std_logic_vector((N-1) downto 0);
+	y27:		out	std_logic_vector((N-1) downto 0);
+	y28:		out	std_logic_vector((N-1) downto 0);
+	y29:		out	std_logic_vector((N-1) downto 0);
+	y30:		out	std_logic_vector((N-1) downto 0);
+	y31:		out	std_logic_vector((N-1) downto 0);
+	y32:		out	std_logic_vector((N-1) downto 0);
+	y33:		out	std_logic_vector((N-1) downto 0);
+	y34:		out	std_logic_vector((N-1) downto 0);
+	y35:		out	std_logic_vector((N-1) downto 0);
+	y36:		out	std_logic_vector((N-1) downto 0);
+	y37:		out	std_logic_vector((N-1) downto 0);
+	y38:		out	std_logic_vector((N-1) downto 0);
+	y39:		out	std_logic_vector((N-1) downto 0);
+	y40:		out	std_logic_vector((N-1) downto 0);
+	y41:		out	std_logic_vector((N-1) downto 0);
+	y42:		out	std_logic_vector((N-1) downto 0);
+	y43:		out	std_logic_vector((N-1) downto 0);
+	y44:		out	std_logic_vector((N-1) downto 0);
+	y45:		out	std_logic_vector((N-1) downto 0);
+	y46:		out	std_logic_vector((N-1) downto 0);
+	y47:		out	std_logic_vector((N-1) downto 0);
+	y48:		out	std_logic_vector((N-1) downto 0);
+	y49:		out	std_logic_vector((N-1) downto 0);
+	y50:		out	std_logic_vector((N-1) downto 0);
+	y51:		out	std_logic_vector((N-1) downto 0);
+	y52:		out	std_logic_vector((N-1) downto 0);
+	y53:		out	std_logic_vector((N-1) downto 0);
+	y54:		out	std_logic_vector((N-1) downto 0);
+	y55:		out	std_logic_vector((N-1) downto 0);
+	y56:		out	std_logic_vector((N-1) downto 0);
+	y57:		out	std_logic_vector((N-1) downto 0);
+	y58:		out	std_logic_vector((N-1) downto 0);
+	y59:		out	std_logic_vector((N-1) downto 0);
+	y60:		out	std_logic_vector((N-1) downto 0);
+	y61:		out	std_logic_vector((N-1) downto 0);
+	y62:		out	std_logic_vector((N-1) downto 0);
+	y63:		out	std_logic_vector((N-1) downto 0);
+	y64:		out	std_logic_vector((N-1) downto 0);
+	y65:		out	std_logic_vector((N-1) downto 0);
+	y66:		out	std_logic_vector((N-1) downto 0);
+	y67:		out	std_logic_vector((N-1) downto 0);
+	y68:		out	std_logic_vector((N-1) downto 0);
+	y69:		out	std_logic_vector((N-1) downto 0);
+	y70:		out	std_logic_vector((N-1) downto 0);
+	y71:		out	std_logic_vector((N-1) downto 0);
+	y72:		out	std_logic_vector((N-1) downto 0);
+	y73:		out	std_logic_vector((N-1) downto 0);
+	y74:		out	std_logic_vector((N-1) downto 0);
+	y75:		out	std_logic_vector((N-1) downto 0);
+	y76:		out	std_logic_vector((N-1) downto 0);
+	y77:		out	std_logic_vector((N-1) downto 0);
+	y78:		out	std_logic_vector((N-1) downto 0);
+	y79:		out	std_logic_vector((N-1) downto 0);
+	y80:		out	std_logic_vector((N-1) downto 0);
+	y81:		out	std_logic_vector((N-1) downto 0);
+	y82:		out	std_logic_vector((N-1) downto 0);
+	y83:		out	std_logic_vector((N-1) downto 0);
+	y84:		out	std_logic_vector((N-1) downto 0);
+	y85:		out	std_logic_vector((N-1) downto 0);
+	y86:		out	std_logic_vector((N-1) downto 0);
+	y87:		out	std_logic_vector((N-1) downto 0);
+	y88:		out	std_logic_vector((N-1) downto 0);
+	y89:		out	std_logic_vector((N-1) downto 0);
+	y90:		out	std_logic_vector((N-1) downto 0);
+	y91:		out	std_logic_vector((N-1) downto 0);
+	y92:		out	std_logic_vector((N-1) downto 0);
+	y93:		out	std_logic_vector((N-1) downto 0);
+	y94:		out	std_logic_vector((N-1) downto 0);
+	y95:		out	std_logic_vector((N-1) downto 0);
+	y96:		out	std_logic_vector((N-1) downto 0);
+	y97:		out	std_logic_vector((N-1) downto 0);
+	y98:		out	std_logic_vector((N-1) downto 0);
+	y99:		out	std_logic_vector((N-1) downto 0);
+	y100:		out	std_logic_vector((N-1) downto 0);
+	y101:		out	std_logic_vector((N-1) downto 0);
+	y102:		out	std_logic_vector((N-1) downto 0);
+	y103:		out	std_logic_vector((N-1) downto 0);
+	y104:		out	std_logic_vector((N-1) downto 0);
+	y105:		out	std_logic_vector((N-1) downto 0);
+	y106:		out	std_logic_vector((N-1) downto 0);
+	y107:		out	std_logic_vector((N-1) downto 0);
+	y108:		out	std_logic_vector((N-1) downto 0);
+	y109:		out	std_logic_vector((N-1) downto 0);
+	y110:		out	std_logic_vector((N-1) downto 0);
+	y111:		out	std_logic_vector((N-1) downto 0);
+	y112:		out	std_logic_vector((N-1) downto 0);
+	y113:		out	std_logic_vector((N-1) downto 0);
+	y114:		out	std_logic_vector((N-1) downto 0);
+	y115:		out	std_logic_vector((N-1) downto 0);
+	y116:		out	std_logic_vector((N-1) downto 0);
+	y117:		out	std_logic_vector((N-1) downto 0);
+	y118:		out	std_logic_vector((N-1) downto 0);
+	y119:		out	std_logic_vector((N-1) downto 0);
+	y120:		out	std_logic_vector((N-1) downto 0);
+	y121:		out	std_logic_vector((N-1) downto 0);
+	y122:		out	std_logic_vector((N-1) downto 0);
+	y123:		out	std_logic_vector((N-1) downto 0);
+	y124:		out	std_logic_vector((N-1) downto 0);
+	y125:		out	std_logic_vector((N-1) downto 0);
+	y126:		out	std_logic_vector((N-1) downto 0);
+	y127:		out	std_logic_vector((N-1) downto 0);
+	y128:		out	std_logic_vector((N-1) downto 0);
+	y129:		out	std_logic_vector((N-1) downto 0);
+	y130:		out	std_logic_vector((N-1) downto 0);
+	y131:		out	std_logic_vector((N-1) downto 0);
+	y132:		out	std_logic_vector((N-1) downto 0);
+	y133:		out	std_logic_vector((N-1) downto 0);
+	y134:		out	std_logic_vector((N-1) downto 0);
+	y135:		out	std_logic_vector((N-1) downto 0);
+	y136:		out	std_logic_vector((N-1) downto 0);
+	y137:		out	std_logic_vector((N-1) downto 0);
+	y138:		out	std_logic_vector((N-1) downto 0);
+	y139:		out	std_logic_vector((N-1) downto 0);
+	y140:		out	std_logic_vector((N-1) downto 0);
+	y141:		out	std_logic_vector((N-1) downto 0);
+	y142:		out	std_logic_vector((N-1) downto 0);
+	y143:		out	std_logic_vector((N-1) downto 0);
+	y144:		out	std_logic_vector((N-1) downto 0);
+	y145:		out	std_logic_vector((N-1) downto 0);
+	y146:		out	std_logic_vector((N-1) downto 0);
+	y147:		out	std_logic_vector((N-1) downto 0);
+	y148:		out	std_logic_vector((N-1) downto 0);
+	y149:		out	std_logic_vector((N-1) downto 0);
+	y150:		out	std_logic_vector((N-1) downto 0);
+	y151:		out	std_logic_vector((N-1) downto 0);
+	y152:		out	std_logic_vector((N-1) downto 0);
+	y153:		out	std_logic_vector((N-1) downto 0);
+	y154:		out	std_logic_vector((N-1) downto 0);
+	y155:		out	std_logic_vector((N-1) downto 0);
+	y156:		out	std_logic_vector((N-1) downto 0);
+	y157:		out	std_logic_vector((N-1) downto 0);
+	y158:		out	std_logic_vector((N-1) downto 0);
+	y159:		out	std_logic_vector((N-1) downto 0);
+	y160:		out	std_logic_vector((N-1) downto 0);
+	y161:		out	std_logic_vector((N-1) downto 0);
+	y162:		out	std_logic_vector((N-1) downto 0);
+	y163:		out	std_logic_vector((N-1) downto 0);
+	y164:		out	std_logic_vector((N-1) downto 0);
+	y165:		out	std_logic_vector((N-1) downto 0);
+	y166:		out	std_logic_vector((N-1) downto 0);
+	y167:		out	std_logic_vector((N-1) downto 0);
+	y168:		out	std_logic_vector((N-1) downto 0);
+	y169:		out	std_logic_vector((N-1) downto 0);
+	y170:		out	std_logic_vector((N-1) downto 0);
+	y171:		out	std_logic_vector((N-1) downto 0);
+	y172:		out	std_logic_vector((N-1) downto 0);
+	y173:		out	std_logic_vector((N-1) downto 0);
+	y174:		out	std_logic_vector((N-1) downto 0);
+	y175:		out	std_logic_vector((N-1) downto 0);
+	y176:		out	std_logic_vector((N-1) downto 0);
+	y177:		out	std_logic_vector((N-1) downto 0);
+	y178:		out	std_logic_vector((N-1) downto 0);
+	y179:		out	std_logic_vector((N-1) downto 0);
+	y180:		out	std_logic_vector((N-1) downto 0);
+	y181:		out	std_logic_vector((N-1) downto 0);
+	y182:		out	std_logic_vector((N-1) downto 0);
+	y183:		out	std_logic_vector((N-1) downto 0);
+	y184:		out	std_logic_vector((N-1) downto 0);
+	y185:		out	std_logic_vector((N-1) downto 0);
+	y186:		out	std_logic_vector((N-1) downto 0);
+	y187:		out	std_logic_vector((N-1) downto 0);
+	y188:		out	std_logic_vector((N-1) downto 0);
+	y189:		out	std_logic_vector((N-1) downto 0);
+	y190:		out	std_logic_vector((N-1) downto 0);
+	y191:		out	std_logic_vector((N-1) downto 0);
+	y192:		out	std_logic_vector((N-1) downto 0);
+	y193:		out	std_logic_vector((N-1) downto 0);
+	y194:		out	std_logic_vector((N-1) downto 0);
+	y195:		out	std_logic_vector((N-1) downto 0);
+	y196:		out	std_logic_vector((N-1) downto 0);
+	y197:		out	std_logic_vector((N-1) downto 0);
+	y198:		out	std_logic_vector((N-1) downto 0);
+	y199:		out	std_logic_vector((N-1) downto 0);
+	y200:		out	std_logic_vector((N-1) downto 0);
+	y201:		out	std_logic_vector((N-1) downto 0);
+	y202:		out	std_logic_vector((N-1) downto 0);
+	y203:		out	std_logic_vector((N-1) downto 0);
+	y204:		out	std_logic_vector((N-1) downto 0);
+	y205:		out	std_logic_vector((N-1) downto 0);
+	y206:		out	std_logic_vector((N-1) downto 0);
+	y207:		out	std_logic_vector((N-1) downto 0);
+	y208:		out	std_logic_vector((N-1) downto 0);
+	y209:		out	std_logic_vector((N-1) downto 0);
+	y210:		out	std_logic_vector((N-1) downto 0);
+	y211:		out	std_logic_vector((N-1) downto 0);
+	y212:		out	std_logic_vector((N-1) downto 0);
+	y213:		out	std_logic_vector((N-1) downto 0);
+	y214:		out	std_logic_vector((N-1) downto 0);
+	y215:		out	std_logic_vector((N-1) downto 0);
+	y216:		out	std_logic_vector((N-1) downto 0);
+	y217:		out	std_logic_vector((N-1) downto 0);
+	y218:		out	std_logic_vector((N-1) downto 0);
+	y219:		out	std_logic_vector((N-1) downto 0);
+	y220:		out	std_logic_vector((N-1) downto 0);
+	y221:		out	std_logic_vector((N-1) downto 0);
+	y222:		out	std_logic_vector((N-1) downto 0);
+	y223:		out	std_logic_vector((N-1) downto 0);
+	y224:		out	std_logic_vector((N-1) downto 0);
+	y225:		out	std_logic_vector((N-1) downto 0);
+	y226:		out	std_logic_vector((N-1) downto 0);
+	y227:		out	std_logic_vector((N-1) downto 0);
+	y228:		out	std_logic_vector((N-1) downto 0);
+	y229:		out	std_logic_vector((N-1) downto 0);
+	y230:		out	std_logic_vector((N-1) downto 0);
+	y231:		out	std_logic_vector((N-1) downto 0);
+	y232:		out	std_logic_vector((N-1) downto 0);
+	y233:		out	std_logic_vector((N-1) downto 0);
+	y234:		out	std_logic_vector((N-1) downto 0);
+	y235:		out	std_logic_vector((N-1) downto 0);
+	y236:		out	std_logic_vector((N-1) downto 0);
+	y237:		out	std_logic_vector((N-1) downto 0);
+	y238:		out	std_logic_vector((N-1) downto 0);
+	y239:		out	std_logic_vector((N-1) downto 0);
+	y240:		out	std_logic_vector((N-1) downto 0);
+	y241:		out	std_logic_vector((N-1) downto 0);
+	y242:		out	std_logic_vector((N-1) downto 0);
+	y243:		out	std_logic_vector((N-1) downto 0);
+	y244:		out	std_logic_vector((N-1) downto 0);
+	y245:		out	std_logic_vector((N-1) downto 0);
+	y246:		out	std_logic_vector((N-1) downto 0);
+	y247:		out	std_logic_vector((N-1) downto 0);
+	y248:		out	std_logic_vector((N-1) downto 0);
+	y249:		out	std_logic_vector((N-1) downto 0);
+	y250:		out	std_logic_vector((N-1) downto 0);
+	y251:		out	std_logic_vector((N-1) downto 0);
+	y252:		out	std_logic_vector((N-1) downto 0);
+	y253:		out	std_logic_vector((N-1) downto 0);
+	y254:		out	std_logic_vector((N-1) downto 0);
+	y255:		out	std_logic_vector((N-1) downto 0);
+	address:	in	std_logic_vector(7 downto 0)
+);
+end;
+
+architecture struct_decoderNx256 of decoderNx256 is
+component decoder1x256 is
+port(
+	data:		in	std_logic;
+	y0:			out	std_logic;
+	y1:			out	std_logic;
+	y2:			out	std_logic;
+	y3:			out	std_logic;
+	y4:			out	std_logic;
+	y5:			out	std_logic;
+	y6:			out	std_logic;
+	y7:			out	std_logic;
+	y8:			out	std_logic;
+	y9:			out	std_logic;
+	y10:		out	std_logic;
+	y11:		out	std_logic;
+	y12:		out	std_logic;
+	y13:		out	std_logic;
+	y14:		out	std_logic;
+	y15:		out	std_logic;
+	y16:		out	std_logic;
+	y17:		out	std_logic;
+	y18:		out	std_logic;
+	y19:		out	std_logic;
+	y20:		out	std_logic;
+	y21:		out	std_logic;
+	y22:		out	std_logic;
+	y23:		out	std_logic;
+	y24:		out	std_logic;
+	y25:		out	std_logic;
+	y26:		out	std_logic;
+	y27:		out	std_logic;
+	y28:		out	std_logic;
+	y29:		out	std_logic;
+	y30:		out	std_logic;
+	y31:		out	std_logic;
+	y32:		out	std_logic;
+	y33:		out	std_logic;
+	y34:		out	std_logic;
+	y35:		out	std_logic;
+	y36:		out	std_logic;
+	y37:		out	std_logic;
+	y38:		out	std_logic;
+	y39:		out	std_logic;
+	y40:		out	std_logic;
+	y41:		out	std_logic;
+	y42:		out	std_logic;
+	y43:		out	std_logic;
+	y44:		out	std_logic;
+	y45:		out	std_logic;
+	y46:		out	std_logic;
+	y47:		out	std_logic;
+	y48:		out	std_logic;
+	y49:		out	std_logic;
+	y50:		out	std_logic;
+	y51:		out	std_logic;
+	y52:		out	std_logic;
+	y53:		out	std_logic;
+	y54:		out	std_logic;
+	y55:		out	std_logic;
+	y56:		out	std_logic;
+	y57:		out	std_logic;
+	y58:		out	std_logic;
+	y59:		out	std_logic;
+	y60:		out	std_logic;
+	y61:		out	std_logic;
+	y62:		out	std_logic;
+	y63:		out	std_logic;
+	y64:		out	std_logic;
+	y65:		out	std_logic;
+	y66:		out	std_logic;
+	y67:		out	std_logic;
+	y68:		out	std_logic;
+	y69:		out	std_logic;
+	y70:		out	std_logic;
+	y71:		out	std_logic;
+	y72:		out	std_logic;
+	y73:		out	std_logic;
+	y74:		out	std_logic;
+	y75:		out	std_logic;
+	y76:		out	std_logic;
+	y77:		out	std_logic;
+	y78:		out	std_logic;
+	y79:		out	std_logic;
+	y80:		out	std_logic;
+	y81:		out	std_logic;
+	y82:		out	std_logic;
+	y83:		out	std_logic;
+	y84:		out	std_logic;
+	y85:		out	std_logic;
+	y86:		out	std_logic;
+	y87:		out	std_logic;
+	y88:		out	std_logic;
+	y89:		out	std_logic;
+	y90:		out	std_logic;
+	y91:		out	std_logic;
+	y92:		out	std_logic;
+	y93:		out	std_logic;
+	y94:		out	std_logic;
+	y95:		out	std_logic;
+	y96:		out	std_logic;
+	y97:		out	std_logic;
+	y98:		out	std_logic;
+	y99:		out	std_logic;
+	y100:		out	std_logic;
+	y101:		out	std_logic;
+	y102:		out	std_logic;
+	y103:		out	std_logic;
+	y104:		out	std_logic;
+	y105:		out	std_logic;
+	y106:		out	std_logic;
+	y107:		out	std_logic;
+	y108:		out	std_logic;
+	y109:		out	std_logic;
+	y110:		out	std_logic;
+	y111:		out	std_logic;
+	y112:		out	std_logic;
+	y113:		out	std_logic;
+	y114:		out	std_logic;
+	y115:		out	std_logic;
+	y116:		out	std_logic;
+	y117:		out	std_logic;
+	y118:		out	std_logic;
+	y119:		out	std_logic;
+	y120:		out	std_logic;
+	y121:		out	std_logic;
+	y122:		out	std_logic;
+	y123:		out	std_logic;
+	y124:		out	std_logic;
+	y125:		out	std_logic;
+	y126:		out	std_logic;
+	y127:		out	std_logic;
+	y128:		out	std_logic;
+	y129:		out	std_logic;
+	y130:		out	std_logic;
+	y131:		out	std_logic;
+	y132:		out	std_logic;
+	y133:		out	std_logic;
+	y134:		out	std_logic;
+	y135:		out	std_logic;
+	y136:		out	std_logic;
+	y137:		out	std_logic;
+	y138:		out	std_logic;
+	y139:		out	std_logic;
+	y140:		out	std_logic;
+	y141:		out	std_logic;
+	y142:		out	std_logic;
+	y143:		out	std_logic;
+	y144:		out	std_logic;
+	y145:		out	std_logic;
+	y146:		out	std_logic;
+	y147:		out	std_logic;
+	y148:		out	std_logic;
+	y149:		out	std_logic;
+	y150:		out	std_logic;
+	y151:		out	std_logic;
+	y152:		out	std_logic;
+	y153:		out	std_logic;
+	y154:		out	std_logic;
+	y155:		out	std_logic;
+	y156:		out	std_logic;
+	y157:		out	std_logic;
+	y158:		out	std_logic;
+	y159:		out	std_logic;
+	y160:		out	std_logic;
+	y161:		out	std_logic;
+	y162:		out	std_logic;
+	y163:		out	std_logic;
+	y164:		out	std_logic;
+	y165:		out	std_logic;
+	y166:		out	std_logic;
+	y167:		out	std_logic;
+	y168:		out	std_logic;
+	y169:		out	std_logic;
+	y170:		out	std_logic;
+	y171:		out	std_logic;
+	y172:		out	std_logic;
+	y173:		out	std_logic;
+	y174:		out	std_logic;
+	y175:		out	std_logic;
+	y176:		out	std_logic;
+	y177:		out	std_logic;
+	y178:		out	std_logic;
+	y179:		out	std_logic;
+	y180:		out	std_logic;
+	y181:		out	std_logic;
+	y182:		out	std_logic;
+	y183:		out	std_logic;
+	y184:		out	std_logic;
+	y185:		out	std_logic;
+	y186:		out	std_logic;
+	y187:		out	std_logic;
+	y188:		out	std_logic;
+	y189:		out	std_logic;
+	y190:		out	std_logic;
+	y191:		out	std_logic;
+	y192:		out	std_logic;
+	y193:		out	std_logic;
+	y194:		out	std_logic;
+	y195:		out	std_logic;
+	y196:		out	std_logic;
+	y197:		out	std_logic;
+	y198:		out	std_logic;
+	y199:		out	std_logic;
+	y200:		out	std_logic;
+	y201:		out	std_logic;
+	y202:		out	std_logic;
+	y203:		out	std_logic;
+	y204:		out	std_logic;
+	y205:		out	std_logic;
+	y206:		out	std_logic;
+	y207:		out	std_logic;
+	y208:		out	std_logic;
+	y209:		out	std_logic;
+	y210:		out	std_logic;
+	y211:		out	std_logic;
+	y212:		out	std_logic;
+	y213:		out	std_logic;
+	y214:		out	std_logic;
+	y215:		out	std_logic;
+	y216:		out	std_logic;
+	y217:		out	std_logic;
+	y218:		out	std_logic;
+	y219:		out	std_logic;
+	y220:		out	std_logic;
+	y221:		out	std_logic;
+	y222:		out	std_logic;
+	y223:		out	std_logic;
+	y224:		out	std_logic;
+	y225:		out	std_logic;
+	y226:		out	std_logic;
+	y227:		out	std_logic;
+	y228:		out	std_logic;
+	y229:		out	std_logic;
+	y230:		out	std_logic;
+	y231:		out	std_logic;
+	y232:		out	std_logic;
+	y233:		out	std_logic;
+	y234:		out	std_logic;
+	y235:		out	std_logic;
+	y236:		out	std_logic;
+	y237:		out	std_logic;
+	y238:		out	std_logic;
+	y239:		out	std_logic;
+	y240:		out	std_logic;
+	y241:		out	std_logic;
+	y242:		out	std_logic;
+	y243:		out	std_logic;
+	y244:		out	std_logic;
+	y245:		out	std_logic;
+	y246:		out	std_logic;
+	y247:		out	std_logic;
+	y248:		out	std_logic;
+	y249:		out	std_logic;
+	y250:		out	std_logic;
+	y251:		out	std_logic;
+	y252:		out	std_logic;
+	y253:		out	std_logic;
+	y254:		out	std_logic;
+	y255:		out	std_logic;
+	address:	in	std_logic_vector(7 downto 0)
+);
+
+end component;
+
+begin
+	u1: for i in (N-1) downto 0 generate
+		u:  decoder1x256 port map(
+				data	=> data(i),
+				y0		=> y0(i),
+				y1		=> y1(i),
+				y2		=> y2(i),
+				y3		=> y3(i),
+				y4		=> y4(i),
+				y5		=> y5(i),
+				y6		=> y6(i),
+				y7		=> y7(i),
+				y8		=> y8(i),
+				y9		=> y9(i),
+				y10		=> y10(i),
+				y11		=> y11(i),
+				y12		=> y12(i),
+				y13		=> y13(i),
+				y14		=> y14(i),
+				y15		=> y15(i),
+				y16		=> y16(i),
+				y17		=> y17(i),
+				y18		=> y18(i),
+				y19		=> y19(i),
+				y20		=> y20(i),
+				y21		=> y21(i),
+				y22		=> y22(i),
+				y23		=> y23(i),
+				y24		=> y24(i),
+				y25		=> y25(i),
+				y26		=> y26(i),
+				y27		=> y27(i),
+				y28		=> y28(i),
+				y29		=> y29(i),
+				y30		=> y30(i),
+				y31		=> y31(i),
+				y32		=> y32(i),
+				y33		=> y33(i),
+				y34		=> y34(i),
+				y35		=> y35(i),
+				y36		=> y36(i),
+				y37		=> y37(i),
+				y38		=> y38(i),
+				y39		=> y39(i),
+				y40		=> y40(i),
+				y41		=> y41(i),
+				y42		=> y42(i),
+				y43		=> y43(i),
+				y44		=> y44(i),
+				y45		=> y45(i),
+				y46		=> y46(i),
+				y47		=> y47(i),
+				y48		=> y48(i),
+				y49		=> y49(i),
+				y50		=> y50(i),
+				y51		=> y51(i),
+				y52		=> y52(i),
+				y53		=> y53(i),
+				y54		=> y54(i),
+				y55		=> y55(i),
+				y56		=> y56(i),
+				y57		=> y57(i),
+				y58		=> y58(i),
+				y59		=> y59(i),
+				y60		=> y60(i),
+				y61		=> y61(i),
+				y62		=> y62(i),
+				y63		=> y63(i),
+				y64		=> y64(i),
+				y65		=> y65(i),
+				y66		=> y66(i),
+				y67		=> y67(i),
+				y68		=> y68(i),
+				y69		=> y69(i),
+				y70		=> y70(i),
+				y71		=> y71(i),
+				y72		=> y72(i),
+				y73		=> y73(i),
+				y74		=> y74(i),
+				y75		=> y75(i),
+				y76		=> y76(i),
+				y77		=> y77(i),
+				y78		=> y78(i),
+				y79		=> y79(i),
+				y80		=> y80(i),
+				y81		=> y81(i),
+				y82		=> y82(i),
+				y83		=> y83(i),
+				y84		=> y84(i),
+				y85		=> y85(i),
+				y86		=> y86(i),
+				y87		=> y87(i),
+				y88		=> y88(i),
+				y89		=> y89(i),
+				y90		=> y90(i),
+				y91		=> y91(i),
+				y92		=> y92(i),
+				y93		=> y93(i),
+				y94		=> y94(i),
+				y95		=> y95(i),
+				y96		=> y96(i),
+				y97		=> y97(i),
+				y98		=> y98(i),
+				y99		=> y99(i),
+				y100	=> y100(i),
+				y101	=> y101(i),
+				y102	=> y102(i),
+				y103	=> y103(i),
+				y104	=> y104(i),
+				y105	=> y105(i),
+				y106	=> y106(i),
+				y107	=> y107(i),
+				y108	=> y108(i),
+				y109	=> y109(i),
+				y110	=> y110(i),
+				y111	=> y111(i),
+				y112	=> y112(i),
+				y113	=> y113(i),
+				y114	=> y114(i),
+				y115	=> y115(i),
+				y116	=> y116(i),
+				y117	=> y117(i),
+				y118	=> y118(i),
+				y119	=> y119(i),
+				y120	=> y120(i),
+				y121	=> y121(i),
+				y122	=> y122(i),
+				y123	=> y123(i),
+				y124	=> y124(i),
+				y125	=> y125(i),
+				y126	=> y126(i),
+				y127	=> y127(i),
+				y128	=> y128(i),
+				y129	=> y129(i),
+				y130	=> y130(i),
+				y131	=> y131(i),
+				y132	=> y132(i),
+				y133	=> y133(i),
+				y134	=> y134(i),
+				y135	=> y135(i),
+				y136	=> y136(i),
+				y137	=> y137(i),
+				y138	=> y138(i),
+				y139	=> y139(i),
+				y140	=> y140(i),
+				y141	=> y141(i),
+				y142	=> y142(i),
+				y143	=> y143(i),
+				y144	=> y144(i),
+				y145	=> y145(i),
+				y146	=> y146(i),
+				y147	=> y147(i),
+				y148	=> y148(i),
+				y149	=> y149(i),
+				y150	=> y150(i),
+				y151	=> y151(i),
+				y152	=> y152(i),
+				y153	=> y153(i),
+				y154	=> y154(i),
+				y155	=> y155(i),
+				y156	=> y156(i),
+				y157	=> y157(i),
+				y158	=> y158(i),
+				y159	=> y159(i),
+				y160	=> y160(i),
+				y161	=> y161(i),
+				y162	=> y162(i),
+				y163	=> y163(i),
+				y164	=> y164(i),
+				y165	=> y165(i),
+				y166	=> y166(i),
+				y167	=> y167(i),
+				y168	=> y168(i),
+				y169	=> y169(i),
+				y170	=> y170(i),
+				y171	=> y171(i),
+				y172	=> y172(i),
+				y173	=> y173(i),
+				y174	=> y174(i),
+				y175	=> y175(i),
+				y176	=> y176(i),
+				y177	=> y177(i),
+				y178	=> y178(i),
+				y179	=> y179(i),
+				y180	=> y180(i),
+				y181	=> y181(i),
+				y182	=> y182(i),
+				y183	=> y183(i),
+				y184	=> y184(i),
+				y185	=> y185(i),
+				y186	=> y186(i),
+				y187	=> y187(i),
+				y188	=> y188(i),
+				y189	=> y189(i),
+				y190	=> y190(i),
+				y191	=> y191(i),
+				y192	=> y192(i),
+				y193	=> y193(i),
+				y194	=> y194(i),
+				y195	=> y195(i),
+				y196	=> y196(i),
+				y197	=> y197(i),
+				y198	=> y198(i),
+				y199	=> y199(i),
+				y200	=> y200(i),
+				y201	=> y201(i),
+				y202	=> y202(i),
+				y203	=> y203(i),
+				y204	=> y204(i),
+				y205	=> y205(i),
+				y206	=> y206(i),
+				y207	=> y207(i),
+				y208	=> y208(i),
+				y209	=> y209(i),
+				y210	=> y210(i),
+				y211	=> y211(i),
+				y212	=> y212(i),
+				y213	=> y213(i),
+				y214	=> y214(i),
+				y215	=> y215(i),
+				y216	=> y216(i),
+				y217	=> y217(i),
+				y218	=> y218(i),
+				y219	=> y219(i),
+				y220	=> y220(i),
+				y221	=> y221(i),
+				y222	=> y222(i),
+				y223	=> y223(i),
+				y224	=> y224(i),
+				y225	=> y225(i),
+				y226	=> y226(i),
+				y227	=> y227(i),
+				y228	=> y228(i),
+				y229	=> y229(i),
+				y230	=> y230(i),
+				y231	=> y231(i),
+				y232	=> y232(i),
+				y233	=> y233(i),
+				y234	=> y234(i),
+				y235	=> y235(i),
+				y236	=> y236(i),
+				y237	=> y237(i),
+				y238	=> y238(i),
+				y239	=> y239(i),
+				y240	=> y240(i),
+				y241	=> y241(i),
+				y242	=> y242(i),
+				y243	=> y243(i),
+				y244	=> y244(i),
+				y245	=> y245(i),
+				y246	=> y246(i),
+				y247	=> y247(i),
+				y248	=> y248(i),
+				y249	=> y249(i),
+				y250	=> y250(i),
+				y251	=> y251(i),
+				y252	=> y252(i),
+				y253	=> y253(i),
+				y254	=> y254(i),
+				y255	=> y255(i),
+				address	=> address
+			);
+	end generate u1;
+end;
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+entity counterN is
+generic(
+	N:	positive
+);
+port(
+	clock:			in	std_logic;
+	carry_in:		in	std_logic;
+	clock_enable:	in	std_logic;
+	resetn:			in	std_logic;
+	output:			out	std_logic_vector((N-1) downto 0);
+	carry_out:		out	std_logic
+);
+end;
+
+architecture struct_counterN of counterN is
+component incrementerN is
+generic(
+	N:	positive
+);
+port(
+	input:		in	std_logic_vector((N-1) downto 0);
+	carry_in:	in	std_logic;
+	sum:		out	std_logic_vector((N-1) downto 0);
+	carry_out:	out	std_logic
+);
+end component;
+
+component andNbit is
+generic(
+	N:	positive
+);
+port(
+	input:	in	std_logic_vector((N-1) downto 0);
+	y:		out	std_logic
+);
+end component;
+
+component synchronous_latchN is
+generic(
+	N:	positive
+);
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic_vector((N-1) downto 0);
+	q:				out	std_logic_vector((N-1) downto 0)
+);
+end component;
+
+signal	counter_out:		std_logic_vector(N downto 0);
+
+signal	incrementer_out:	std_logic_vector(N downto 0);
+
+signal	all_ones:			std_logic;
+
+begin
+	u1: incrementerN
+			generic map(
+				N => N
+			)
+			port map(
+				input => counter_out((N-1) downto 0),
+				carry_in => carry_in,
+				sum => incrementer_out((N-1) downto 0),
+				carry_out => incrementer_out(N)
+			);
+
+	u2: synchronous_latchN
+			generic map(
+				N => (N + 1)
+			)
+			port map(
+				rstn => resetn,
+				clock => clock,
+				clock_enable => clock_enable,
+				d => incrementer_out,
+				q => counter_out
+			);
+
+	u3: andNbit
+			generic map(
+				N => N
+			)
+			port map(
+				input => counter_out((N-1) downto 0),
+				y => all_ones
+			);
+
+	carry_out <= all_ones and carry_in;
+	output <= counter_out((N-1) downto 0);
+end;
diff --git a/testsuite/gna/issue30/definitions.vhdl b/testsuite/gna/issue30/definitions.vhdl
new file mode 100644
index 000000000..da1c4f514
--- /dev/null
+++ b/testsuite/gna/issue30/definitions.vhdl
@@ -0,0 +1,1230 @@
+library	ieee;

+use		ieee.std_logic_1164.all;

+--use		ieee.std_logic_arith.all;

+

+package definitions is

+

+-- flag bits

+constant	carry_bit:				integer := 0;

+constant	add_sub_bit:			integer := 1;

+constant	parity_overflow_bit:	integer := 2;

+constant	half_carry_bit:	  		integer := 4;

+constant	zero_bit:		  		integer := 6;

+constant	sign_bit:		  		integer := 7;

+

+-- 8 bit register numbers

+constant	B:				  		std_logic_vector(3 downto 0)	:= "0000";

+constant	B3:						std_logic_vector(2 downto 0)	:= "000";	-- keep GHDL happy,

+																				-- won't accept

+																				-- bitslice of

+																				-- constant in case

+																				-- statements

+constant	C:				  		std_logic_vector(3 downto 0)	:= "0001";

+constant	C3:						std_logic_vector(2 downto 0)	:= "001";

+constant	D:				  		std_logic_vector(3 downto 0)	:= "0010";

+constant	D3:						std_logic_vector(2 downto 0)	:= "010";

+constant	E:				  		std_logic_vector(3 downto 0)	:= "0011";

+constant	E3:						std_logic_vector(2 downto 0)	:= "011";

+constant	H:				  		std_logic_vector(3 downto 0)	:= "0100";

+constant	H3:						std_logic_vector(2 downto 0)	:= "100";

+constant	L:				  		std_logic_vector(3 downto 0)	:= "0101";

+constant	L3:						std_logic_vector(2 downto 0)	:= "101";

+constant	memory_register:  		std_logic_vector(3 downto 0)	:= "0110";

+constant	memory_register3:		std_logic_vector(2 downto 0)	:= "110";

+constant	A:			   	  		std_logic_vector(3 downto 0)	:= "0111";

+constant	A3:						std_logic_vector(2 downto 0)	:= "111";

+

+constant	one_register:  	  		std_logic_vector(3 downto 0)	:= "1000";	-- fixed constant of

+																				-- one at register 8

+																				-- in secondary ALU

+																				-- register file

+

+

+constant	zero_register: 	  		std_logic_vector(3 downto 0)	:= "1001";

+constant	indexhigh:	   	  		std_logic_vector(3 downto 0)	:= "1010";

+constant	indexlow:	   	   		std_logic_vector(3 downto 0)	:= "1011";

+constant	bitreg:			   		std_logic_vector(3 downto 0)	:= "1100";

+constant	not_bitreg:		   		std_logic_vector(3 downto 0)	:= "1101";

+constant	SPhigh:		   	   		std_logic_vector(3 downto 0)	:= "1110";

+constant	SPlow:		   	   		std_logic_vector(3 downto 0)	:= "1111";

+

+constant	call_return_interrupt:	std_logic_vector(3 downto 0)	:= "1000";	-- for sending call

+																				-- return address

+																				-- thru ALU, primary

+																				-- register only

+constant	flags_register:	   		std_logic_vector(3 downto 0)	:= "1000";	-- for sending flags

+																				-- thru ALU -

+																				-- multiplexed with

+																				-- call return,

+																				-- primary register

+																				-- only

+constant	interrupt_register:		std_logic_vector(3 downto 0)	:= "1000";	-- for sending

+																				-- interrupt

+																				-- register thru

+																				-- ALU - multiplexed

+																				-- with call return,

+																				-- primary register

+																				-- only

+

+

+

+-- ALU operation codes

+constant	add_operation: 	 		std_logic_vector(4 downto 0)	:= "00000";	-- add without carry

+constant	adc_operation: 	 		std_logic_vector(4 downto 0)	:= "00001";	-- add with carry

+constant	sub_operation: 			std_logic_vector(4 downto 0)	:= "00010";	-- subtract without

+																				-- carry

+constant	sbc_operation: 			std_logic_vector(4 downto 0)	:= "00011";	-- subtract with

+																				-- carry

+constant	and_operation: 			std_logic_vector(4 downto 0)	:= "00100";	-- and

+constant	xor_operation: 			std_logic_vector(4 downto 0)	:= "00101";	-- xor

+constant	or_operation:  			std_logic_vector(4 downto 0)	:= "00110";	-- or

+constant	cmp_operation: 			std_logic_vector(4 downto 0)	:= "00111";	-- compare (subtract

+																				-- and discard

+																				-- results, set

+																				-- flags

+constant	rlc_operation: 			std_logic_vector(4 downto 0)	:= "01000";	-- RLC

+constant	rrc_operation: 			std_logic_vector(4 downto 0)	:= "01001";	-- RRC

+constant	rl_operation: 			std_logic_vector(4 downto 0)	:= "01010";	-- RLA

+constant	rr_operation: 			std_logic_vector(4 downto 0)	:= "01011";	-- RRA

+constant	daa_operation: 			std_logic_vector(4 downto 0)	:= "01100";	-- DAA

+constant	cpl_operation: 			std_logic_vector(4 downto 0)	:= "01101";	-- CPL

+constant	scf_operation: 			std_logic_vector(4 downto 0)	:= "01110";	-- SCF

+constant	ccf_operation: 			std_logic_vector(4 downto 0)	:= "01111";	-- CCF

+constant	sla_operation: 			std_logic_vector(4 downto 0)	:= "10000";	-- SLA

+constant	sra_operation: 			std_logic_vector(4 downto 0)	:= "10001";	-- SRA

+constant	sll_operation: 			std_logic_vector(4 downto 0)	:= "10010";	-- SLL

+constant	srl_operation:	 		std_logic_vector(4 downto 0)	:= "10011";	-- SRL

+constant	bit_operation:			std_logic_vector(4 downto 0)	:= "10100";	-- BIT

+constant	res_operation: 			std_logic_vector(4 downto 0)	:= "10101";	-- RES

+constant	set_operation:			std_logic_vector(4 downto 0)	:= "10110";	-- SET

+constant	in16_operation:			std_logic_vector(4 downto 0)	:= "10111";	-- in r, (c)

+constant	rld_operation:			std_logic_vector(4 downto 0)	:= "11000";	-- RLD

+constant	rrd_operation:			std_logic_vector(4 downto 0)	:= "11001";	-- RRD

+constant	blockterm16_operation:	std_logic_vector(4 downto 0)	:= "11010";	-- block instruction

+																				-- termination:

+																				-- P/V = 0 when

+																				-- BC = 0

+

+-- ALU operation flags masks - the ones that change are listed, others are masked out

+constant	alu_mask:				std_logic_vector(7 downto 0)	:= (	carry_bit => '1',

+																			add_sub_bit => '1',

+																			parity_overflow_bit => '1',

+																			half_carry_bit => '1',

+																			zero_bit => '1',

+																			sign_bit => '1',

+																			others => '0'

+																			);

+

+-- Block operation load masks

+constant	block_load_mask:		std_logic_vector(7 downto 0)	:= (	add_sub_bit => '1',

+																			parity_overflow_bit => '1',

+																			half_carry_bit => '1',

+																			others => '0'

+																			);

+

+constant	block_compare_mask1:	std_logic_vector(7 downto 0)	:= (	add_sub_bit => '1',

+																			half_carry_bit => '1',

+																			zero_bit => '1',

+																			sign_bit => '1',

+																			others => '0'

+																			);

+

+constant	block_compare_mask2:	std_logic_vector(7 downto 0)	:= (	parity_overflow_bit => '1',

+																			others => '0'

+																			);

+

+constant	block_io_mask:			std_logic_vector(7 downto 0)	:= (	add_sub_bit => '1',

+																			zero_bit => '1',

+																			others => '0'

+																			);

+

+-- bit masks for bit oriented instructions

+constant	bit7mask:	std_logic_vector(7 downto 0)	:= (7 => '1', others => '0');

+constant	bit6mask:	std_logic_vector(7 downto 0)	:= (6 => '1', others => '0');

+constant	bit5mask:	std_logic_vector(7 downto 0)	:= (5 => '1', others => '0');

+constant	bit4mask:	std_logic_vector(7 downto 0)	:= (4 => '1', others => '0');

+constant	bit3mask:	std_logic_vector(7 downto 0)	:= (3 => '1', others => '0');

+constant	bit2mask:	std_logic_vector(7 downto 0)	:= (2 => '1', others => '0');

+constant	bit1mask:	std_logic_vector(7 downto 0)	:= (1 => '1', others => '0');

+constant	bit0mask:	std_logic_vector(7 downto 0)	:= (0 => '1', others => '0');

+

+-- address bus selector

+constant	address_bus_source_BC:			std_logic_vector(3 downto 0)	:= x"0";

+constant	address_bus_source_DE:			std_logic_vector(3 downto 0)	:= x"1";

+constant	address_bus_source_HL:			std_logic_vector(3 downto 0)	:= x"2";

+constant	address_bus_source_SP:			std_logic_vector(3 downto 0)	:= x"3";

+constant	address_bus_source_PC:			std_logic_vector(3 downto 0)	:= x"4";

+constant	address_bus_source_operand:		std_logic_vector(3 downto 0)	:= x"5";

+constant	address_bus_source_operand1:	std_logic_vector(3 downto 0)	:= x"6";

+constant	address_bus_source_port8:		std_logic_vector(3 downto 0)	:= x"7";

+constant	address_bus_source_index:		std_logic_vector(3 downto 0)	:= x"8";

+

+-- program counter selector

+constant	pc_source_next:					std_logic_vector(3 downto 0)	:= x"0";	-- PC + 1

+constant	pc_source_operand:				std_logic_vector(3 downto 0)	:= x"1";	-- operand

+constant	pc_source_HL:					std_logic_vector(3 downto 0)	:= x"2";	-- PCHL

+constant	pc_source_return:				std_logic_vector(3 downto 0)	:= x"3";	-- return

+																						-- address

+constant	pc_source_next_next:			std_logic_vector(3 downto 0)	:= x"4";	-- PC + 2

+constant	pc_source_rst:					std_logic_vector(3 downto 0)	:= x"5";	-- RST nn

+constant	pc_source_index_register:		std_logic_vector(3 downto 0)	:= x"6";	-- PCIX and PCIY

+constant	pc_source_jr:					std_logic_vector(3 downto 0)	:= x"7";	-- JR offset

+constant	pc_source_block_repeat:			std_logic_vector(3 downto 0)	:= x"8";	-- for

+																						-- interrupted

+																						-- block repeats

+constant	pc_source_reset:				std_logic_vector(3 downto 0)	:= x"f";	-- sets PC

+																						-- vector

+																						-- after reset

+

+-- initial program counter.  Zilog spec says it is always zero, but often autojump hardware is

+-- implemented to change this.  I have the luxury of specifying the initial program counter as I see

+-- fit.

+constant	PC_start_address:				std_logic_vector(15 downto 0)	:= x"0000";

+

+-- SP source mux input definitins

+constant	SPsource_databus:				std_logic_vector(1 downto 0)	:= "00";	-- select

+																						-- databus

+constant	SPsource_increment:				std_logic_vector(1 downto 0)	:= "01";	-- select SP + 1

+constant	SPsource_decrement:				std_logic_vector(1 downto 0)	:= "10";	-- select SP - 1

+

+-- data output mux selectors

+constant	data_out_selector_databus:			std_logic_vector(2 downto 0)	:= "000";	-- select

+																							-- databus

+constant	data_out_selector_H:				std_logic_vector(2 downto 0)	:= "001";	-- select

+																							-- temporary

+																							-- register

+																							-- for

+																							-- register

+																							-- H

+constant	data_out_selector_L:				std_logic_vector(2 downto 0)	:= "010";	-- select

+																							-- temporary

+																							-- register

+																							-- for

+																							-- register

+																							-- L

+constant	data_out_selector_indexhigh:		std_logic_vector(2 downto 0)	:= "011";	-- select

+																							-- temporary

+																							-- register

+																							-- for

+																							-- register

+																							-- IXhigh

+constant	data_out_selector_indexlow:			std_logic_vector(2 downto 0)	:= "100";	-- select

+																							-- temporary

+																							-- register

+																							-- for

+																							-- register

+																							-- IXlow

+constant	data_out_selector_rrd_rld_output:	std_logic_vector(2 downto 0)	:= "101";	-- select

+																							-- secondary

+																							-- ALU

+																							-- output

+																							-- (RLD and

+																							-- RRD)

+

+-- select among return address, flags, or interrupt vector register to go through the ALU.

+constant	selectRetAddr:					std_logic_vector(1 downto 0)	:= "00";	-- select return

+																						-- address

+constant	selectFlags:					std_logic_vector(1 downto 0)	:= "01";	-- select flags

+constant	selectInterruptVector:			std_logic_vector(1 downto 0)	:= "10";	-- select

+																						-- interrupt

+																						-- vector

+																						-- register

+

+-- operand register selection

+constant	operandSelectLow:				std_logic	:= '0';	-- selects operand register low byte

+constant	operandSelectHigh:				std_logic	:= '1';	-- selects operand register bigh byte

+

+-- assertion and deassertion of control lines

+constant	assert_m1:						std_logic	:= '1';

+constant	deassert_m1:					std_logic	:= '0';

+constant	assert_write:					std_logic	:= '1';

+constant	deassert_write:					std_logic	:= '0';

+constant	assert_read:					std_logic	:= '1';

+constant	deassert_read:					std_logic	:= '0';

+constant	assert_iorq:					std_logic	:= '1';

+constant	deassert_iorq:					std_logic	:= '0';

+constant	assert_mreq:					std_logic	:= '1';

+constant	deassert_mreq:					std_logic	:= '0';

+

+-- Index register selection

+constant	SelectIndexIX:					std_logic	:= '0';

+constant	SelectIndexIY:					std_logic	:= '1';

+

+-- Return address byte selection

+constant	RetAddrLow:						std_logic	:= '0';

+constant	RetAddrHigh:					std_logic	:= '1';

+

+-- Enable and disable writing to instruction register

+constant	disableOpcodeWrite:				std_logic	:= '0';

+constant	enableOpcodeWrite:	   			std_logic	:= '1';

+

+-- Enable and disable XCHG hardware

+constant	disableXCHG:					std_logic	:= '0';

+constant	enableXCHG:			   			std_logic	:= '1';

+

+-- For master and slave control of the address, data and control busses

+constant	masterControl:					std_logic	:= '1';

+constant	slaveControl:					std_logic	:= '0';

+

+constant	deassert_halted:				std_logic	:= '0';

+constant	assert_halted:					std_logic	:= '1';

+

+-- For control of source of ALU operation

+constant	selectVHDL_ALU_operation:		std_logic	:= '0';

+constant	selectOpcode_ALU_operation:		std_logic	:= '1';

+

+-- for source of primary and secondary ALU operand registers

+constant	selectOpcodeRegister:			std_logic	:= '0';

+constant	selectVHDLRegister:				std_logic	:= '1';

+

+-- for register saving

+constant	save:							std_logic	:= '1';

+constant	DontSave:						std_logic	:= '0';

+

+-- for choosing source of flags data

+constant	ALUflags:						std_logic	:= '0';

+constant	POPflags:						std_logic	:= '1';

+

+-- for general clock enable and disable

+constant	clockEnable:					std_logic	:= '1';

+constant	clockDisable:					std_logic	:= '0';

+

+-- for invalid instruction detector

+constant	safe:							std_logic	:= '0';

+constant	fail:							std_logic	:= '1';

+

+-- for interrupt modes

+constant	IM_0:							std_logic_vector(1 downto 0)	:= "00";

+constant	IM_1:							std_logic_vector(1 downto 0)	:= "01";

+constant	IM_2:							std_logic_vector(1 downto 0)	:= "10";

+

+constant	width_is_8:						positive := 8;

+

+-- State numbers.  Done this way so state numbers can be stored and used as a return address

+

+-- common to all opcodes

+

+

+constant	initialise:					std_logic_vector(11 downto 0)	:= x"000";	-- initialise

+																					-- processor,

+																	 				-- enters on

+																	 				-- rising edge of

+																	 				-- clk_out

+constant	initialise1:				std_logic_vector(11 downto 0)	:= x"001";	-- second

+																					-- initialisation

+																	 				-- state

+constant	initialise2:				std_logic_vector(11 downto 0)	:= x"002";	-- third

+																					-- initialisation

+																	 				-- state

+constant	initialise3:				std_logic_vector(11 downto 0)	:= x"003";	-- fourth

+																					-- initialisation

+																	 				-- state

+constant	opcode:						std_logic_vector(11 downto 0)	:= x"004";	-- assert pc address

+																					-- drivers and

+																					-- m1n = '0'

+																					-- for 1st opcode

+																					-- byte, rising edge

+																					-- of clock, done

+																					-- in last state of

+																					-- previous

+																					-- instruction

+constant	opcode_mreq:				std_logic_vector(11 downto 0)	:= x"005";	-- assert

+																					-- mreqn = '0' and

+																					-- rdn = '0' on

+																					-- falling edge of

+																					-- clock

+constant	opcode_latch:				std_logic_vector(11 downto 0)	:= x"006";	-- latch opcode byte

+																					-- on next rising

+																					-- edge of clock

+																					-- with waitn = '1',

+																					-- rising edge of

+																					-- clock

+constant	decode_opcode:				std_logic_vector(11 downto 0)	:= x"007";	-- decode first

+																					-- opcode

+constant	invalid:					std_logic_vector(11 downto 0)	:= x"008";	-- state name for

+																					-- invalid return

+																					-- state and illegal

+																					-- instruction

+

+-- states for BUSRQ handling

+constant	busrq:						std_logic_vector(11 downto 0)	:= x"009";

+

+-- New PC state for use with jr, jp, ret, call, rst

+constant	NewPC:						std_logic_vector(11 downto 0)	:= x"00f";

+

+-- opcodes in order presented by z80.info/decoding.  Number of states (initially) conforms

+-- to number of clock cycles as advertised in the Z80 data sheet.  States are added because

+-- I process information on both positive and negative transitions of the clock.  These

+-- will be removed if they are not needed. Memory and port I/O operations are always

+-- initiated at the positive going edge of the clock.  Instructions that do not appear here

+-- are processed entirely during the decoding phase of operation.

+

+-- NOP states, 4 clock cycles, all required for timing loops, 1 m1 cycle

+constant	nop4:						std_logic_vector(11 downto 0)	:= x"010";	-- instruction

+																					-- origin + 3 rising

+																					-- edges

+constant	nop5:						std_logic_vector(11 downto 0)	:= x"011";	-- instruction

+																					-- origin + 4 rising

+																					-- edges

+

+-- DJNZ, 8/13 cycles (met, not met), 1 m1 cycle

+constant	djnz4:						std_logic_vector(11 downto 0)	:= x"030";

+

+-- JR, 12 cycles, 1 m1 cycle

+constant	jr4:						std_logic_vector(11 downto 0)	:= x"040";

+constant	jr5:						std_logic_vector(11 downto 0)	:= x"041";

+constant	jr6:						std_logic_vector(11 downto 0)	:= x"042";

+constant	jr7:						std_logic_vector(11 downto 0)	:= x"043";

+

+-- JR conditional, 12/7 cycles (met/not met), 1 m1 cycle

+-- need one state to test condition, transfer control to jr code

+-- Number of cycles = one or two more than jr

+constant	jrcc4:						std_logic_vector(11 downto 0)	:= x"050";

+constant	jrcc5:						std_logic_vector(11 downto 0)	:= x"051";

+

+-- LD rp, immediate, 10 cycles, 1 m1 cycle

+constant	ldrpi4:						std_logic_vector(11 downto 0)	:= x"060";

+constant	ldrpi5:						std_logic_vector(11 downto 0)	:= x"061";

+

+-- ADD HL, rp, 11 clock cycles, 1 m1 cycle

+constant	addhlrp4:					std_logic_vector(11 downto 0)	:= x"070";

+constant	addhlrp5:					std_logic_vector(11 downto 0)	:= x"071";

+

+-- LDAX rp, 7 cycles, 1 m1 cycle

+constant	ldax4:						std_logic_vector(11 downto 0)	:= x"080";

+constant	ldax5:						std_logic_vector(11 downto 0)	:= x"081";

+

+-- STAX rp, 7 cycles, 1 m1 cycle

+constant	stax4:						std_logic_vector(11 downto 0)	:= x"090";

+constant	stax5:						std_logic_vector(11 downto 0)	:= x"091";

+

+-- LDA nn, 13 cycles, 1 m1 cycle

+constant	lda4:						std_logic_vector(11 downto 0)	:= x"0a0";

+constant	lda5:						std_logic_vector(11 downto 0)	:= x"0a1";

+constant	lda6:						std_logic_vector(11 downto 0)	:= x"0a2";

+constant	lda7:						std_logic_vector(11 downto 0)	:= x"0a3";

+

+-- STA nn, 13 cycles, 1 m1 cycle

+constant	sta4:						std_logic_vector(11 downto 0)	:= x"0b0";

+constant	sta5:						std_logic_vector(11 downto 0)	:= x"0b1";

+

+

+-- LHLD (nn), 16 cycles, 1 m1 cycle

+constant	ldhl4:						std_logic_vector(11 downto 0)	:= x"0c0";

+constant	ldhl5:						std_logic_vector(11 downto 0)	:= x"0c1";

+constant	ldhl6:						std_logic_vector(11 downto 0)	:= x"0c2";

+constant	ldhl7:						std_logic_vector(11 downto 0)	:= x"0c3";

+constant	ldhl8:						std_logic_vector(11 downto 0)	:= x"0c4";

+

+-- SHLD (nn), 16 cycles, 1 m1 cycle

+constant	sthl4:						std_logic_vector(11 downto 0)	:= x"0d0";

+constant	sthl5:						std_logic_vector(11 downto 0)	:= x"0d1";

+constant	sthl6:						std_logic_vector(11 downto 0)	:= x"0d2";

+constant	sthl7:						std_logic_vector(11 downto 0)	:= x"0d3";

+

+-- 16 bit increment/decrement, 6 cycles, 1 m1 cycle

+constant	incdec16_4:					std_logic_vector(11 downto 0)	:= x"0e0";

+constant	incdec16_5:					std_logic_vector(11 downto 0)	:= x"0e1";

+constant	incdec16_6:					std_logic_vector(11 downto 0)	:= x"0e2";

+constant	incdec16_7:					std_logic_vector(11 downto 0)	:= x"0e3";

+

+-- 8 bit register/memory increment/decrement, 11 cycles, 1 m1 cycle

+constant	incdec8_4:					std_logic_vector(11 downto 0)	:= x"0f0";

+

+-- 8 bit load immediate, 7 cycles, 1 m1 cycle

+constant	ldi4:						std_logic_vector(11 downto 0)	:= x"100";

+

+-- DAA, 4 cycles, 1 m1 cycle

+constant	daa4:						std_logic_vector(11 downto 0)	:= x"110";

+constant	daa5:						std_logic_vector(11 downto 0)	:= x"111";

+constant	daa6:						std_logic_vector(11 downto 0)	:= x"112";

+constant	daa7:						std_logic_vector(11 downto 0)	:= x"113";

+

+-- SCF/CCF, 4 cycles, 1 m1 cycle

+-- main processing done at instruction decoder stage

+constant	scf_ccf_save:				std_logic_vector(11 downto 0)	:= x"120";

+

+-- inter-register 8 bit loading, 4 cycles, 1 m1 cycle

+constant	irld4:						std_logic_vector(11 downto 0)	:= x"130";

+constant	irld5:						std_logic_vector(11 downto 0)	:= x"131";

+

+-- HALT, 4 cycles, 1 m1 cycle, may trim this to three

+-- cycles initially plus one cycle per instruction thereafter

+constant	halt4:						std_logic_vector(11 downto 0)	:= x"140";

+constant	halt5:						std_logic_vector(11 downto 0)	:= x"141";

+constant	halt6:						std_logic_vector(11 downto 0)	:= x"142";

+constant	halt7:						std_logic_vector(11 downto 0)	:= x"143";

+

+-- alu operations on registers, 4 cycles, 1 m1 cycle

+constant	alu4:						std_logic_vector(11 downto 0)	:= x"150";

+

+-- POP, 10 cycles, 1 m1 cycle

+constant	pop4:						std_logic_vector(11 downto 0)	:= x"160";

+constant	pop5:						std_logic_vector(11 downto 0)	:= x"161";

+constant	pop6:						std_logic_vector(11 downto 0)	:= x"162";

+constant	pop7:						std_logic_vector(11 downto 0)	:= x"163";

+constant	pop8:						std_logic_vector(11 downto 0)	:= x"164";

+

+-- RET unconditional, 10 cycles, 1 m1 cycle

+constant	ret4:						std_logic_vector(11 downto 0)	:= x"170";

+constant	ret5:						std_logic_vector(11 downto 0)	:= x"171";

+constant	ret6:						std_logic_vector(11 downto 0)	:= x"172";

+constant	ret7:						std_logic_vector(11 downto 0)	:= x"173";

+constant	ret8:						std_logic_vector(11 downto 0)	:= x"174";

+constant	ret9:						std_logic_vector(11 downto 0)	:= x"175";

+

+-- JP HL, 4 cycles,1 m1 cycle

+constant	jphl4:						std_logic_vector(11 downto 0)	:= x"180";

+

+-- LD SP, HL, 6 cycles, 1 m1 cycle

+constant	sphl4:						std_logic_vector(11 downto 0)	:= x"190";

+

+-- JP conditional, 10 cycles met or not, 1 m1 cycle

+-- use one state to determine if ret is to be executed, then transfer to JP unconditional if so.

+constant	jpcc4:						std_logic_vector(11 downto 0)	:= x"1a0";

+constant	jpcc5:						std_logic_vector(11 downto 0)	:= x"1a1";

+

+-- JP unconditional, 10 cycles, 1 m1 cycle

+constant	jp4:						std_logic_vector(11 downto 0)	:= x"1b0";

+constant	jp5:						std_logic_vector(11 downto 0)	:= x"1b1";

+constant	jp6:						std_logic_vector(11 downto 0)	:= x"1b2";

+

+-- CB prefix, must obtain next instruction byte

+constant	cb4:						std_logic_vector(11 downto 0)	:= x"1c0";

+constant	cb5:						std_logic_vector(11 downto 0)	:= x"1c1";

+

+-- save results from CB prefixed opcodes other than BIT, SET, and RES

+constant	bitsave:					std_logic_vector(11 downto 0)	:= x"1e0";

+

+-- common state for save and load 16 bit registers with ED prefix

+constant	rp16io:						std_logic_vector(11 downto 0)	:= x"1f0";

+

+-- BIT

+constant	bit6:						std_logic_vector(11 downto 0)	:= x"200";

+constant	bit7:						std_logic_vector(11 downto 0)	:= x"201";

+

+-- RES

+constant	res6:						std_logic_vector(11 downto 0)	:= x"210";

+

+-- SET

+constant	set6:						std_logic_vector(11 downto 0)	:= x"220";

+

+-- end of CB prefixed opcodes

+

+-- 8 bit output of accumulator to 8 bit port address, 11 cycles, 1 m1 cycle

+constant	out4:						std_logic_vector(11 downto 0)	:= x"230";

+constant	out5:						std_logic_vector(11 downto 0)	:= x"231";

+constant	out6:						std_logic_vector(11 downto 0)	:= x"232";

+constant	out7:						std_logic_vector(11 downto 0)	:= x"233";

+constant	out8:						std_logic_vector(11 downto 0)	:= x"234";

+

+-- 8 bit input of accumulator from 8 bit port address, 11 cycles, 1 m1 cycle

+constant	in4:						std_logic_vector(11 downto 0)	:= x"240";

+constant	in5:						std_logic_vector(11 downto 0)	:= x"241";

+constant	in6:						std_logic_vector(11 downto 0)	:= x"242";

+constant	in7:						std_logic_vector(11 downto 0)	:= x"243";

+

+-- EX (SP), HL, 19 cycles, 1 m1 cycle

+constant	xthl4:						std_logic_vector(11 downto 0)	:= x"250";

+constant	xthl5:						std_logic_vector(11 downto 0)	:= x"251";

+constant	xthl6:						std_logic_vector(11 downto 0)	:= x"252";

+constant	xthl7:						std_logic_vector(11 downto 0)	:= x"253";

+constant	xthl8:						std_logic_vector(11 downto 0)	:= x"254";

+constant	xthl9:						std_logic_vector(11 downto 0)	:= x"255";

+constant	xthl10:						std_logic_vector(11 downto 0)	:= x"256";

+

+-- DI, 4 cycles, 1 m1 cycle

+constant	di4:						std_logic_vector(11 downto 0)	:= x"270";

+constant	di5:						std_logic_vector(11 downto 0)	:= x"271";

+constant	di6:						std_logic_vector(11 downto 0)	:= x"272";

+constant	di7:						std_logic_vector(11 downto 0)	:= x"273";

+

+-- EI, 4 cycles, 1 m1 cycle

+constant	ei4:						std_logic_vector(11 downto 0)	:= x"280";

+constant	ei5:						std_logic_vector(11 downto 0)	:= x"281";

+constant	ei6:						std_logic_vector(11 downto 0)	:= x"282";

+constant	ei7:						std_logic_vector(11 downto 0)	:= x"283";

+

+-- PUSH, 10 cycles, 1 m1 cycle

+constant	push4:						std_logic_vector(11 downto 0)	:= x"2a0";

+constant	push5:						std_logic_vector(11 downto 0)	:= x"2a1";

+constant	push6:						std_logic_vector(11 downto 0)	:= x"2a2";

+constant	push7:						std_logic_vector(11 downto 0)	:= x"2a3";

+

+-- CALL unconditional, 17 clock cycles, 1 m1 cycle

+constant	call4:						std_logic_vector(11 downto 0)	:= x"2b0";

+constant	call5:						std_logic_vector(11 downto 0)	:= x"2b1";

+constant	call6:						std_logic_vector(11 downto 0)	:= x"2b2";

+constant	call7:						std_logic_vector(11 downto 0)	:= x"2b3";

+constant	call8:						std_logic_vector(11 downto 0)	:= x"2b4";

+

+-- end of DD prefixed opcodes

+

+-- ED prefix, must obtain next instruction byte

+constant	ed4:						std_logic_vector(11 downto 0)	:= x"2c0";

+constant	ed5:						std_logic_vector(11 downto 0)	:= x"2c1";

+constant	ed6:						std_logic_vector(11 downto 0)	:= x"2c2";

+constant	ed7:						std_logic_vector(11 downto 0)	:= x"2c3";

+constant	ed8:						std_logic_vector(11 downto 0)	:= x"2c4";

+constant	ed9:						std_logic_vector(11 downto 0)	:= x"2c5";

+constant	ed10:						std_logic_vector(11 downto 0)	:= x"2c6";

+

+-- 8 bit input to register from a 16 bit port address, 12 cycles, 1 m1 cycle

+constant	in16_5:						std_logic_vector(11 downto 0)	:= x"2d0";

+constant	in16_6:						std_logic_vector(11 downto 0)	:= x"2d1";

+

+-- 8 bit output to register from a 16 bit port address, 12 cycles, 1 m1 cycle

+constant	out16_5:					std_logic_vector(11 downto 0)	:= x"2e0";

+constant	out16_6:					std_logic_vector(11 downto 0)	:= x"2e1";

+

+-- 16 bit ADC

+constant	adc_sbc_16_5:				std_logic_vector(11 downto 0)	:= x"2f0";

+

+-- store register pair to immediate address

+constant	strp16_5:					std_logic_vector(11 downto 0)	:= x"300";

+constant	strp16_6:					std_logic_vector(11 downto 0)	:= x"301";

+

+-- load register pair from immediate address

+constant	ldrp16_5:					std_logic_vector(11 downto 0)	:= x"310";

+constant	ldrp16_6:					std_logic_vector(11 downto 0)	:= x"311";

+constant	ldrp16_7:					std_logic_vector(11 downto 0)	:= x"312";

+

+-- NEG

+constant	neg6:						std_logic_vector(11 downto 0)	:= x"320";

+

+-- RETN

+constant	retn6:						std_logic_vector(11 downto 0)	:= x"330";

+constant	retn7:						std_logic_vector(11 downto 0)	:= x"331";

+constant	retn8:						std_logic_vector(11 downto 0)	:= x"332";

+constant	retn9:						std_logic_vector(11 downto 0)	:= x"333";

+constant	retn10:						std_logic_vector(11 downto 0)	:= x"334";

+constant	retn11:						std_logic_vector(11 downto 0)	:= x"335";

+constant	retn12:						std_logic_vector(11 downto 0)	:= x"336";

+constant	retn13:						std_logic_vector(11 downto 0)	:= x"337";

+constant	retn14:						std_logic_vector(11 downto 0)	:= x"338";

+constant	retn15:						std_logic_vector(11 downto 0)	:= x"339";

+constant	retn16:						std_logic_vector(11 downto 0)	:= x"33a";

+constant	retn17:						std_logic_vector(11 downto 0)	:= x"33b";

+constant	retn18:						std_logic_vector(11 downto 0)	:= x"33c";

+constant	retn19:						std_logic_vector(11 downto 0)	:= x"33d";

+constant	retn20:						std_logic_vector(11 downto 0)	:= x"33e";

+constant	retn21:						std_logic_vector(11 downto 0)	:= x"33f";

+constant	retn22:						std_logic_vector(11 downto 0)	:= x"340";

+constant	retn23:						std_logic_vector(11 downto 0)	:= x"342";

+constant	retn24:						std_logic_vector(11 downto 0)	:= x"343";

+constant	retn25:						std_logic_vector(11 downto 0)	:= x"344";

+

+-- RETI

+constant	reti6:						std_logic_vector(11 downto 0)	:= x"350";

+constant	reti7:						std_logic_vector(11 downto 0)	:= x"351";

+constant	reti8:						std_logic_vector(11 downto 0)	:= x"352";

+constant	reti9:						std_logic_vector(11 downto 0)	:= x"353";

+constant	reti10:						std_logic_vector(11 downto 0)	:= x"354";

+constant	reti11:						std_logic_vector(11 downto 0)	:= x"355";

+constant	reti12:						std_logic_vector(11 downto 0)	:= x"356";

+constant	reti13:						std_logic_vector(11 downto 0)	:= x"357";

+constant	reti14:						std_logic_vector(11 downto 0)	:= x"358";

+constant	reti15:						std_logic_vector(11 downto 0)	:= x"359";

+constant	reti16:						std_logic_vector(11 downto 0)	:= x"35a";

+constant	reti17:						std_logic_vector(11 downto 0)	:= x"35b";

+constant	reti18:						std_logic_vector(11 downto 0)	:= x"35c";

+constant	reti19:						std_logic_vector(11 downto 0)	:= x"35d";

+constant	reti20:						std_logic_vector(11 downto 0)	:= x"35e";

+constant	reti21:						std_logic_vector(11 downto 0)	:= x"35f";

+constant	reti22:						std_logic_vector(11 downto 0)	:= x"360";

+constant	reti23:						std_logic_vector(11 downto 0)	:= x"361";

+constant	reti24:						std_logic_vector(11 downto 0)	:= x"362";

+constant	reti25:						std_logic_vector(11 downto 0)	:= x"363";

+

+-- IM n

+constant	im0_6:						std_logic_vector(11 downto 0)	:= x"370";

+constant	im0_7:						std_logic_vector(11 downto 0)	:= x"371";

+constant	im0_8:						std_logic_vector(11 downto 0)	:= x"372";

+constant	im0_9:						std_logic_vector(11 downto 0)	:= x"373";

+constant	im0_10:						std_logic_vector(11 downto 0)	:= x"374";

+constant	im0_11:						std_logic_vector(11 downto 0)	:= x"375";

+constant	im0_12:						std_logic_vector(11 downto 0)	:= x"376";

+constant	im0_13:						std_logic_vector(11 downto 0)	:= x"377";

+

+constant	im1_6:						std_logic_vector(11 downto 0)	:= x"380";

+constant	im1_7:						std_logic_vector(11 downto 0)	:= x"381";

+constant	im1_8:						std_logic_vector(11 downto 0)	:= x"382";

+constant	im1_9:						std_logic_vector(11 downto 0)	:= x"383";

+constant	im1_10:						std_logic_vector(11 downto 0)	:= x"384";

+constant	im1_11:						std_logic_vector(11 downto 0)	:= x"385";

+constant	im1_12:						std_logic_vector(11 downto 0)	:= x"386";

+constant	im1_13:						std_logic_vector(11 downto 0)	:= x"387";

+

+constant	im2_6:						std_logic_vector(11 downto 0)	:= x"390";

+constant	im2_7:						std_logic_vector(11 downto 0)	:= x"391";

+constant	im2_8:						std_logic_vector(11 downto 0)	:= x"392";

+constant	im2_9:						std_logic_vector(11 downto 0)	:= x"393";

+constant	im2_10:						std_logic_vector(11 downto 0)	:= x"394";

+constant	im2_11:						std_logic_vector(11 downto 0)	:= x"395";

+constant	im2_12:						std_logic_vector(11 downto 0)	:= x"396";

+constant	im2_13:						std_logic_vector(11 downto 0)	:= x"397";

+

+-- LD I, A

+constant	ldia5:						std_logic_vector(11 downto 0)	:= x"3a0";

+constant	ldia6:						std_logic_vector(11 downto 0)	:= x"3a1";

+constant	ldia7:						std_logic_vector(11 downto 0)	:= x"3a2";

+constant	ldia8:						std_logic_vector(11 downto 0)	:= x"3a3";

+constant	ldia9:						std_logic_vector(11 downto 0)	:= x"3a4";

+constant	ldia10:						std_logic_vector(11 downto 0)	:= x"3a5";

+constant	ldia11:						std_logic_vector(11 downto 0)	:= x"3a6";

+constant	ldia12:						std_logic_vector(11 downto 0)	:= x"3a7";

+constant	ldia13:						std_logic_vector(11 downto 0)	:= x"3a8";

+constant	ldia14:						std_logic_vector(11 downto 0)	:= x"3a9";

+

+-- LD R, A, ignore this instruction

+

+-- LD A, I

+constant	ldai5:						std_logic_vector(11 downto 0)	:= x"3b0";

+constant	ldai6:						std_logic_vector(11 downto 0)	:= x"3b1";

+constant	ldai7:						std_logic_vector(11 downto 0)	:= x"3b2";

+constant	ldai8:						std_logic_vector(11 downto 0)	:= x"3b3";

+constant	ldai9:						std_logic_vector(11 downto 0)	:= x"3b4";

+constant	ldai10:						std_logic_vector(11 downto 0)	:= x"3b5";

+constant	ldai11:						std_logic_vector(11 downto 0)	:= x"3b6";

+constant	ldai12:						std_logic_vector(11 downto 0)	:= x"3b7";

+constant	ldai13:						std_logic_vector(11 downto 0)	:= x"3b8";

+constant	ldai14:						std_logic_vector(11 downto 0)	:= x"3b9";

+

+-- LD A, R, ignore this instruction

+

+-- RRD and RLD

+constant	rrd_rld5:					std_logic_vector(11 downto 0)	:= x"3c0";

+

+-- Block instructions

+

+-- LDI

+constant	bldi5:						std_logic_vector(11 downto 0)	:= x"3d0";

+constant	bldi6:						std_logic_vector(11 downto 0)	:= x"3d1";

+constant	bldi7:						std_logic_vector(11 downto 0)	:= x"3d2";

+constant	bldi8:						std_logic_vector(11 downto 0)	:= x"3d3";

+constant	bldi9:						std_logic_vector(11 downto 0)	:= x"3d4";

+constant	bldi10:						std_logic_vector(11 downto 0)	:= x"3d5";

+constant	bldi11:						std_logic_vector(11 downto 0)	:= x"3d6";

+constant	bldi12:						std_logic_vector(11 downto 0)	:= x"3d7";

+constant	bldi13:						std_logic_vector(11 downto 0)	:= x"3d8";

+constant	bldi14:						std_logic_vector(11 downto 0)	:= x"3d9";

+

+-- CPI

+constant	bcpi5:						std_logic_vector(11 downto 0)	:= x"3e0";

+constant	bcpi6:						std_logic_vector(11 downto 0)	:= x"3e1";

+constant	bcpi7:						std_logic_vector(11 downto 0)	:= x"3e2";

+constant	bcpi8:						std_logic_vector(11 downto 0)	:= x"3e3";

+constant	bcpi9:						std_logic_vector(11 downto 0)	:= x"3e4";

+constant	bcpi10:						std_logic_vector(11 downto 0)	:= x"3e5";

+constant	bcpi11:						std_logic_vector(11 downto 0)	:= x"3e6";

+

+-- INI

+constant	bini5:						std_logic_vector(11 downto 0)	:= x"3f0";

+constant	bini6:						std_logic_vector(11 downto 0)	:= x"3f1";

+constant	bini7:						std_logic_vector(11 downto 0)	:= x"3f2";

+constant	bini8:						std_logic_vector(11 downto 0)	:= x"3f3";

+constant	bini9:						std_logic_vector(11 downto 0)	:= x"3f4";

+constant	bini10:						std_logic_vector(11 downto 0)	:= x"3f5";

+constant	bini11:						std_logic_vector(11 downto 0)	:= x"3f6";

+

+-- OUTI

+constant	bouti5:						std_logic_vector(11 downto 0)	:= x"400";

+constant	bouti6:						std_logic_vector(11 downto 0)	:= x"401";

+constant	bouti7:						std_logic_vector(11 downto 0)	:= x"402";

+constant	bouti8:						std_logic_vector(11 downto 0)	:= x"403";

+constant	bouti9:						std_logic_vector(11 downto 0)	:= x"404";

+constant	bouti10:					std_logic_vector(11 downto 0)	:= x"405";

+constant	bouti11:					std_logic_vector(11 downto 0)	:= x"406";

+constant	bouti12:					std_logic_vector(11 downto 0)	:= x"407";

+

+-- LDD

+constant	bldd5:						std_logic_vector(11 downto 0)	:= x"410";

+constant	bldd6:						std_logic_vector(11 downto 0)	:= x"411";

+constant	bldd7:						std_logic_vector(11 downto 0)	:= x"412";

+constant	bldd8:						std_logic_vector(11 downto 0)	:= x"413";

+constant	bldd9:						std_logic_vector(11 downto 0)	:= x"414";

+constant	bldd10:						std_logic_vector(11 downto 0)	:= x"415";

+constant	bldd11:						std_logic_vector(11 downto 0)	:= x"416";

+constant	bldd12:						std_logic_vector(11 downto 0)	:= x"417";

+constant	bldd13:						std_logic_vector(11 downto 0)	:= x"418";

+

+-- CPD

+constant	bcpd5:						std_logic_vector(11 downto 0)	:= x"420";

+constant	bcpd6:						std_logic_vector(11 downto 0)	:= x"421";

+constant	bcpd7:						std_logic_vector(11 downto 0)	:= x"422";

+constant	bcpd8:						std_logic_vector(11 downto 0)	:= x"423";

+constant	bcpd9:						std_logic_vector(11 downto 0)	:= x"424";

+constant	bcpd10:						std_logic_vector(11 downto 0)	:= x"425";

+constant	bcpd11:						std_logic_vector(11 downto 0)	:= x"426";

+

+-- IND

+constant	bind5:						std_logic_vector(11 downto 0)	:= x"430";

+constant	bind6:						std_logic_vector(11 downto 0)	:= x"431";

+constant	bind7:						std_logic_vector(11 downto 0)	:= x"432";

+constant	bind8:						std_logic_vector(11 downto 0)	:= x"433";

+constant	bind9:						std_logic_vector(11 downto 0)	:= x"434";

+constant	bind10:						std_logic_vector(11 downto 0)	:= x"435";

+constant	bind11:						std_logic_vector(11 downto 0)	:= x"436";

+

+-- OUTD

+constant	boutd5:						std_logic_vector(11 downto 0)	:= x"440";

+constant	boutd6:						std_logic_vector(11 downto 0)	:= x"441";

+constant	boutd7:						std_logic_vector(11 downto 0)	:= x"442";

+constant	boutd8:						std_logic_vector(11 downto 0)	:= x"443";

+constant	boutd9:						std_logic_vector(11 downto 0)	:= x"444";

+constant	boutd10:					std_logic_vector(11 downto 0)	:= x"445";

+constant	boutd11:					std_logic_vector(11 downto 0)	:= x"446";

+

+-- LDIR

+constant	bldir5:						std_logic_vector(11 downto 0)	:= x"450";

+constant	bldir6:						std_logic_vector(11 downto 0)	:= x"451";

+--constant	bldir7:						std_logic_vector(11 downto 0)	:= x"452";

+--constant	bldir8:						std_logic_vector(11 downto 0)	:= x"453";

+--constant	bldir9:			  			std_logic_vector(11 downto 0)	:= x"454";

+--constant	bldir10:					std_logic_vector(11 downto 0)	:= x"455";

+--constant	bldir11:					std_logic_vector(11 downto 0)	:= x"456";

+--constant	bldir12:					std_logic_vector(11 downto 0)	:= x"457";

+--constant	bldir13:					std_logic_vector(11 downto 0)	:= x"458";

+--constant	bldir14:					std_logic_vector(11 downto 0)	:= x"459";

+--constant	bldir15:					std_logic_vector(11 downto 0)	:= x"45a";

+--constant	bldir16:					std_logic_vector(11 downto 0)	:= x"45b";

+--constant	bldir17:					std_logic_vector(11 downto 0)	:= x"45c";

+--constant	bldir18:					std_logic_vector(11 downto 0)	:= x"45d";

+--constant	bldir19:					std_logic_vector(11 downto 0)	:= x"45e";

+--constant	bldir20:					std_logic_vector(11 downto 0)	:= x"45f";

+--constant	bldir21:					std_logic_vector(11 downto 0)	:= x"460";

+--constant	bldir22:					std_logic_vector(11 downto 0)	:= x"461";

+--constant	bldir23:					std_logic_vector(11 downto 0)	:= x"462";

+--constant	bldir24:					std_logic_vector(11 downto 0)	:= x"463";

+--constant	bldir25:					std_logic_vector(11 downto 0)	:= x"464";

+--constant	bldir26:					std_logic_vector(11 downto 0)	:= x"465";

+--constant	bldir27:					std_logic_vector(11 downto 0)	:= x"466";

+--constant	bldir28:					std_logic_vector(11 downto 0)	:= x"467";

+--constant	bldir29:					std_logic_vector(11 downto 0)	:= x"468";

+--constant	bldir30:					std_logic_vector(11 downto 0)	:= x"469";

+--constant	bldir31:					std_logic_vector(11 downto 0)	:= x"46a";

+--constant	bldir32:					std_logic_vector(11 downto 0)	:= x"46b";

+--constant	bldir33:					std_logic_vector(11 downto 0)	:= x"46c";

+--constant	bldir34:					std_logic_vector(11 downto 0)	:= x"46d";

+--constant	bldir35:					std_logic_vector(11 downto 0)	:= x"46e";

+--constant	bldir36:					std_logic_vector(11 downto 0)	:= x"46f";

+--constant	bldir37:					std_logic_vector(11 downto 0)	:= x"470";

+--constant	bldir38:					std_logic_vector(11 downto 0)	:= x"471";

+

+-- CPIR

+constant	bcpir5:						std_logic_vector(11 downto 0)	:= x"480";

+constant	bcpir6:						std_logic_vector(11 downto 0)	:= x"481";

+--constant	bcpir7:						std_logic_vector(11 downto 0)	:= x"482";

+--constant	bcpir8:						std_logic_vector(11 downto 0)	:= x"483";

+--constant	bcpir9:						std_logic_vector(11 downto 0)	:= x"484";

+--constant	bcpir10:					std_logic_vector(11 downto 0)	:= x"485";

+--constant	bcpir11:					std_logic_vector(11 downto 0)	:= x"486";

+--constant	bcpir12:					std_logic_vector(11 downto 0)	:= x"487";

+--constant	bcpir13:					std_logic_vector(11 downto 0)	:= x"488";

+--constant	bcpir14:					std_logic_vector(11 downto 0)	:= x"489";

+--constant	bcpir15:					std_logic_vector(11 downto 0)	:= x"48a";

+--constant	bcpir16:					std_logic_vector(11 downto 0)	:= x"48b";

+--constant	bcpir17:					std_logic_vector(11 downto 0)	:= x"48c";

+--constant	bcpir18:					std_logic_vector(11 downto 0)	:= x"48d";

+--constant	bcpir19:					std_logic_vector(11 downto 0)	:= x"48e";

+--constant	bcpir20:					std_logic_vector(11 downto 0)	:= x"48f";

+--constant	bcpir21:					std_logic_vector(11 downto 0)	:= x"490";

+--constant	bcpir22:					std_logic_vector(11 downto 0)	:= x"491";

+--constant	bcpir23:					std_logic_vector(11 downto 0)	:= x"492";

+--constant	bcpir24:					std_logic_vector(11 downto 0)	:= x"493";

+--constant	bcpir25:					std_logic_vector(11 downto 0)	:= x"494";

+--constant	bcpir26:					std_logic_vector(11 downto 0)	:= x"495";

+--constant	bcpir27:					std_logic_vector(11 downto 0)	:= x"496";

+--constant	bcpir28:					std_logic_vector(11 downto 0)	:= x"497";

+--constant	bcpir29:					std_logic_vector(11 downto 0)	:= x"498";

+--constant	bcpir30:					std_logic_vector(11 downto 0)	:= x"499";

+--constant	bcpir31:					std_logic_vector(11 downto 0)	:= x"49a";

+--constant	bcpir32:					std_logic_vector(11 downto 0)	:= x"49b";

+--constant	bcpir33:					std_logic_vector(11 downto 0)	:= x"49c";

+--constant	bcpir34:					std_logic_vector(11 downto 0)	:= x"49d";

+--constant	bcpir35:					std_logic_vector(11 downto 0)	:= x"49e";

+--constant	bcpir36:					std_logic_vector(11 downto 0)	:= x"49f";

+--constant	bcpir37:					std_logic_vector(11 downto 0)	:= x"4a0";

+--constant	bcpir38:					std_logic_vector(11 downto 0)	:= x"4a1";

+

+-- INIR

+constant	binir5:						std_logic_vector(11 downto 0)	:= x"4b0";

+constant	binir6:						std_logic_vector(11 downto 0)	:= x"4b1";

+--constant	binir7:						std_logic_vector(11 downto 0)	:= x"4b2";

+--constant	binir8:						std_logic_vector(11 downto 0)	:= x"4b3";

+--constant	binir9:						std_logic_vector(11 downto 0)	:= x"4b4";

+--constant	binir10:					std_logic_vector(11 downto 0)	:= x"4b5";

+--constant	binir11:					std_logic_vector(11 downto 0)	:= x"4b6";

+--constant	binir12:					std_logic_vector(11 downto 0)	:= x"4b7";

+--constant	binir13:					std_logic_vector(11 downto 0)	:= x"4b8";

+--constant	binir14:					std_logic_vector(11 downto 0)	:= x"4b9";

+--constant	binir15:					std_logic_vector(11 downto 0)	:= x"4ba";

+--constant	binir16:					std_logic_vector(11 downto 0)	:= x"4bb";

+--constant	binir17:					std_logic_vector(11 downto 0)	:= x"4bc";

+--constant	binir18:					std_logic_vector(11 downto 0)	:= x"4bd";

+--constant	binir19:					std_logic_vector(11 downto 0)	:= x"4be";

+--constant	binir20:					std_logic_vector(11 downto 0)	:= x"4bf";

+--constant	binir21:					std_logic_vector(11 downto 0)	:= x"4c0";

+--constant	binir22:					std_logic_vector(11 downto 0)	:= x"4c1";

+--constant	binir23:					std_logic_vector(11 downto 0)	:= x"4c2";

+--constant	binir24:					std_logic_vector(11 downto 0)	:= x"4c3";

+--constant	binir25:					std_logic_vector(11 downto 0)	:= x"4c4";

+--constant	binir26:					std_logic_vector(11 downto 0)	:= x"4c5";

+--constant	binir27:					std_logic_vector(11 downto 0)	:= x"4c6";

+--constant	binir28:					std_logic_vector(11 downto 0)	:= x"4c7";

+--constant	binir29:					std_logic_vector(11 downto 0)	:= x"4c8";

+--constant	binir30:					std_logic_vector(11 downto 0)	:= x"4c9";

+--constant	binir31:					std_logic_vector(11 downto 0)	:= x"4ca";

+--constant	binir32:					std_logic_vector(11 downto 0)	:= x"4cb";

+--constant	binir33:					std_logic_vector(11 downto 0)	:= x"4cc";

+--constant	binir34:					std_logic_vector(11 downto 0)	:= x"4cd";

+--constant	binir35:					std_logic_vector(11 downto 0)	:= x"4ce";

+--constant	binir36:					std_logic_vector(11 downto 0)	:= x"4cf";

+--constant	binir37:					std_logic_vector(11 downto 0)	:= x"4d0";

+--constant	binir38:					std_logic_vector(11 downto 0)	:= x"4d1";

+

+-- OTIR

+constant	botir5:						std_logic_vector(11 downto 0)	:= x"4e0";

+constant	botir6:						std_logic_vector(11 downto 0)	:= x"4e1";

+--constant	botir7:						std_logic_vector(11 downto 0)	:= x"4e2";

+--constant	botir8:						std_logic_vector(11 downto 0)	:= x"4e3";

+--constant	botir9:						std_logic_vector(11 downto 0)	:= x"4e4";

+--constant	botir10:					std_logic_vector(11 downto 0)	:= x"4e5";

+--constant	botir11:					std_logic_vector(11 downto 0)	:= x"4e6";

+--constant	botir12:					std_logic_vector(11 downto 0)	:= x"4e7";

+--constant	botir13:					std_logic_vector(11 downto 0)	:= x"4e8";

+--constant	botir14:					std_logic_vector(11 downto 0)	:= x"4e9";

+--constant	botir15:					std_logic_vector(11 downto 0)	:= x"4ea";

+--constant	botir16:					std_logic_vector(11 downto 0)	:= x"4eb";

+--constant	botir17:					std_logic_vector(11 downto 0)	:= x"4ec";

+--constant	botir18:					std_logic_vector(11 downto 0)	:= x"4ed";

+--constant	botir19:					std_logic_vector(11 downto 0)	:= x"4ee";

+--constant	botir20:					std_logic_vector(11 downto 0)	:= x"4ef";

+--constant	botir21:					std_logic_vector(11 downto 0)	:= x"4f0";

+--constant	botir22:					std_logic_vector(11 downto 0)	:= x"4f1";

+--constant	botir23:					std_logic_vector(11 downto 0)	:= x"4f2";

+--constant	botir24:					std_logic_vector(11 downto 0)	:= x"4f3";

+--constant	botir25:					std_logic_vector(11 downto 0)	:= x"4f4";

+--constant	botir26:					std_logic_vector(11 downto 0)	:= x"4f5";

+--constant	botir27:					std_logic_vector(11 downto 0)	:= x"4f6";

+--constant	botir28:					std_logic_vector(11 downto 0)	:= x"4f7";

+--constant	botir29:					std_logic_vector(11 downto 0)	:= x"4f8";

+--constant	botir30:					std_logic_vector(11 downto 0)	:= x"4f9";

+--constant	botir31:					std_logic_vector(11 downto 0)	:= x"4fa";

+--constant	botir32:					std_logic_vector(11 downto 0)	:= x"4fb";

+--constant	botir33:					std_logic_vector(11 downto 0)	:= x"4fc";

+--constant	botir34:					std_logic_vector(11 downto 0)	:= x"4fd";

+--constant	botir35:					std_logic_vector(11 downto 0)	:= x"4fe";

+--constant	botir36:					std_logic_vector(11 downto 0)	:= x"4ff";

+--constant	botir37:					std_logic_vector(11 downto 0)	:= x"500";

+--constant	botir38:					std_logic_vector(11 downto 0)	:= x"501";

+

+-- LDDR

+constant	blddr5:						std_logic_vector(11 downto 0)	:= x"510";

+constant	blddr6:						std_logic_vector(11 downto 0)	:= x"511";

+--constant	blddr7:						std_logic_vector(11 downto 0)	:= x"512";

+--constant	blddr8:						std_logic_vector(11 downto 0)	:= x"513";

+--constant	blddr9:						std_logic_vector(11 downto 0)	:= x"514";

+--constant	blddr10:					std_logic_vector(11 downto 0)	:= x"515";

+--constant	blddr11:					std_logic_vector(11 downto 0)	:= x"516";

+--constant	blddr12:					std_logic_vector(11 downto 0)	:= x"517";

+--constant	blddr13:					std_logic_vector(11 downto 0)	:= x"518";

+--constant	blddr14:					std_logic_vector(11 downto 0)	:= x"519";

+--constant	blddr15:					std_logic_vector(11 downto 0)	:= x"51a";

+--constant	blddr16:					std_logic_vector(11 downto 0)	:= x"51b";

+--constant	blddr17:					std_logic_vector(11 downto 0)	:= x"51c";

+--constant	blddr18:					std_logic_vector(11 downto 0)	:= x"51d";

+--constant	blddr19:					std_logic_vector(11 downto 0)	:= x"51e";

+--constant	blddr20:					std_logic_vector(11 downto 0)	:= x"51f";

+--constant	blddr21:					std_logic_vector(11 downto 0)	:= x"520";

+--constant	blddr22:					std_logic_vector(11 downto 0)	:= x"521";

+--constant	blddr23:					std_logic_vector(11 downto 0)	:= x"522";

+--constant	blddr24:					std_logic_vector(11 downto 0)	:= x"523";

+--constant	blddr25:					std_logic_vector(11 downto 0)	:= x"524";

+--constant	blddr26:					std_logic_vector(11 downto 0)	:= x"525";

+--constant	blddr27:					std_logic_vector(11 downto 0)	:= x"526";

+--constant	blddr28:					std_logic_vector(11 downto 0)	:= x"527";

+--constant	blddr29:					std_logic_vector(11 downto 0)	:= x"528";

+--constant	blddr30:					std_logic_vector(11 downto 0)	:= x"529";

+--constant	blddr31:					std_logic_vector(11 downto 0)	:= x"52a";

+--constant	blddr32:					std_logic_vector(11 downto 0)	:= x"52b";

+--constant	blddr33:					std_logic_vector(11 downto 0)	:= x"52c";

+--constant	blddr34:					std_logic_vector(11 downto 0)	:= x"52d";

+--constant	blddr35:					std_logic_vector(11 downto 0)	:= x"52e";

+--constant	blddr36:					std_logic_vector(11 downto 0)	:= x"52f";

+--constant	blddr37:					std_logic_vector(11 downto 0)	:= x"530";

+--constant	blddr38:					std_logic_vector(11 downto 0)	:= x"531";

+

+-- CPDR

+constant	bcpdr5:						std_logic_vector(11 downto 0)	:= x"540";

+constant	bcpdr6:						std_logic_vector(11 downto 0)	:= x"541";

+--constant	bcpdr7:						std_logic_vector(11 downto 0)	:= x"542";

+--constant	bcpdr8:						std_logic_vector(11 downto 0)	:= x"543";

+--constant	bcpdr9:						std_logic_vector(11 downto 0)	:= x"544";

+--constant	bcpdr10:					std_logic_vector(11 downto 0)	:= x"545";

+--constant	bcpdr11:					std_logic_vector(11 downto 0)	:= x"546";

+--constant	bcpdr12:					std_logic_vector(11 downto 0)	:= x"547";

+--constant	bcpdr13:					std_logic_vector(11 downto 0)	:= x"548";

+--constant	bcpdr14:					std_logic_vector(11 downto 0)	:= x"549";

+--constant	bcpdr15:					std_logic_vector(11 downto 0)	:= x"54a";

+--constant	bcpdr16:					std_logic_vector(11 downto 0)	:= x"54b";

+--constant	bcpdr17:					std_logic_vector(11 downto 0)	:= x"54c";

+--constant	bcpdr18:					std_logic_vector(11 downto 0)	:= x"54d";

+--constant	bcpdr19:					std_logic_vector(11 downto 0)	:= x"54e";

+--constant	bcpdr20:					std_logic_vector(11 downto 0)	:= x"54f";

+--constant	bcpdr21:					std_logic_vector(11 downto 0)	:= x"550";

+--constant	bcpdr22:					std_logic_vector(11 downto 0)	:= x"551";

+--constant	bcpdr23:					std_logic_vector(11 downto 0)	:= x"552";

+--constant	bcpdr24:					std_logic_vector(11 downto 0)	:= x"553";

+--constant	bcpdr25:					std_logic_vector(11 downto 0)	:= x"554";

+--constant	bcpdr26:					std_logic_vector(11 downto 0)	:= x"555";

+--constant	bcpdr27:					std_logic_vector(11 downto 0)	:= x"556";

+--constant	bcpdr28:					std_logic_vector(11 downto 0)	:= x"557";

+--constant	bcpdr29:					std_logic_vector(11 downto 0)	:= x"558";

+--constant	bcpdr30:					std_logic_vector(11 downto 0)	:= x"559";

+--constant	bcpdr32:					std_logic_vector(11 downto 0)	:= x"55a";

+--constant	bcpdr33:					std_logic_vector(11 downto 0)	:= x"55b";

+--constant	bcpdr34:					std_logic_vector(11 downto 0)	:= x"55c";

+--constant	bcpdr35:					std_logic_vector(11 downto 0)	:= x"55d";

+--constant	bcpdr36:					std_logic_vector(11 downto 0)	:= x"55e";

+--constant	bcpdr37:					std_logic_vector(11 downto 0)	:= x"55f";

+--constant	bcpdr38:					std_logic_vector(11 downto 0)	:= x"560";

+--constant	bcpdr39:					std_logic_vector(11 downto 0)	:= x"561";

+

+-- INDR

+constant	bindr5:						std_logic_vector(11 downto 0)	:= x"570";

+constant	bindr6:						std_logic_vector(11 downto 0)	:= x"571";

+--constant	bindr7:						std_logic_vector(11 downto 0)	:= x"572";

+--constant	bindr8:						std_logic_vector(11 downto 0)	:= x"573";

+--constant	bindr9:						std_logic_vector(11 downto 0)	:= x"574";

+--constant	bindr13:					std_logic_vector(11 downto 0)	:= x"575";

+--constant	bindr10:					std_logic_vector(11 downto 0)	:= x"576";

+--constant	bindr18:					std_logic_vector(11 downto 0)	:= x"577";

+--constant	bindr12:					std_logic_vector(11 downto 0)	:= x"578";

+--constant	bindr13:					std_logic_vector(11 downto 0)	:= x"579";

+--constant	bindr14:					std_logic_vector(11 downto 0)	:= x"57a";

+--constant	bindr15:					std_logic_vector(11 downto 0)	:= x"57b";

+--constant	bindr16:					std_logic_vector(11 downto 0)	:= x"57c";

+--constant	bindr17:					std_logic_vector(11 downto 0)	:= x"57d";

+--constant	bindr18:					std_logic_vector(11 downto 0)	:= x"57e";

+--constant	bindr19:					std_logic_vector(11 downto 0)	:= x"57f";

+--constant	bindr20:					std_logic_vector(11 downto 0)	:= x"580";

+--constant	bindr21:					std_logic_vector(11 downto 0)	:= x"581";

+--constant	bindr22:					std_logic_vector(11 downto 0)	:= x"582";

+--constant	bindr23:					std_logic_vector(11 downto 0)	:= x"583";

+--constant	bindr24:					std_logic_vector(11 downto 0)	:= x"584";

+--constant	bindr25:					std_logic_vector(11 downto 0)	:= x"585";

+--constant	bindr26:					std_logic_vector(11 downto 0)	:= x"586";

+--constant	bindr27:					std_logic_vector(11 downto 0)	:= x"587";

+--constant	bindr28:					std_logic_vector(11 downto 0)	:= x"588";

+--constant	bindr29:					std_logic_vector(11 downto 0)	:= x"589";

+--constant	bindr30:					std_logic_vector(11 downto 0)	:= x"58a";

+--constant	bindr31:					std_logic_vector(11 downto 0)	:= x"58b";

+--constant	bindr32:					std_logic_vector(11 downto 0)	:= x"58c";

+--constant	bindr33:					std_logic_vector(11 downto 0)	:= x"58d";

+--constant	bindr34:					std_logic_vector(11 downto 0)	:= x"58e";

+--constant	bindr35:					std_logic_vector(11 downto 0)	:= x"58f";

+--constant	bindr36:					std_logic_vector(11 downto 0)	:= x"590";

+--constant	bindr37:					std_logic_vector(11 downto 0)	:= x"591";

+

+-- OTDR

+constant	botdr5:						std_logic_vector(11 downto 0)	:= x"5a0";

+constant	botdr6:						std_logic_vector(11 downto 0)	:= x"5a1";

+--constant	botdr7:						std_logic_vector(11 downto 0)	:= x"5a2";

+--constant	botdr8:						std_logic_vector(11 downto 0)	:= x"5a3";

+--constant	botdr9:						std_logic_vector(11 downto 0)	:= x"5a4";

+--constant	botdr10:					std_logic_vector(11 downto 0)	:= x"5a5";

+--constant	botdr11:					std_logic_vector(11 downto 0)	:= x"5a6";

+--constant	botdr12:					std_logic_vector(11 downto 0)	:= x"5a7";

+--constant	botdr13:					std_logic_vector(11 downto 0)	:= x"5a8";

+--constant	botdr14:					std_logic_vector(11 downto 0)	:= x"5a9";

+--constant	botdr15:					std_logic_vector(11 downto 0)	:= x"5aa";

+--constant	botdr16:					std_logic_vector(11 downto 0)	:= x"5ab";

+--constant	botdr17:					std_logic_vector(11 downto 0)	:= x"5ac";

+--constant	botdr18:					std_logic_vector(11 downto 0)	:= x"5ad";

+--constant	botdr19:					std_logic_vector(11 downto 0)	:= x"5ae";

+--constant	botdr20:					std_logic_vector(11 downto 0)	:= x"5af";

+--constant	botdr21:					std_logic_vector(11 downto 0)	:= x"5b0";

+--constant	botdr22:					std_logic_vector(11 downto 0)	:= x"5b1";

+--constant	botdr23:					std_logic_vector(11 downto 0)	:= x"5b2";

+--constant	botdr24:					std_logic_vector(11 downto 0)	:= x"5b3";

+--constant	botdr25:					std_logic_vector(11 downto 0)	:= x"5b4";

+--constant	botdr26:					std_logic_vector(11 downto 0)	:= x"5b5";

+--constant	botdr27:					std_logic_vector(11 downto 0)	:= x"5b6";

+--constant	botdr28:					std_logic_vector(11 downto 0)	:= x"5b7";

+--constant	botdr29:					std_logic_vector(11 downto 0)	:= x"5b8";

+--constant	botdr30:					std_logic_vector(11 downto 0)	:= x"5b9";

+--constant	botdr31:					std_logic_vector(11 downto 0)	:= x"5ba";

+--constant	botdr32:					std_logic_vector(11 downto 0)	:= x"5bb";

+--constant	botdr33:					std_logic_vector(11 downto 0)	:= x"5bc";

+--constant	botdr34:					std_logic_vector(11 downto 0)	:= x"5bd";

+--constant	botdr35:					std_logic_vector(11 downto 0)	:= x"5be";

+--constant	botdr36:					std_logic_vector(11 downto 0)	:= x"5bf";

+--constant	botdr37:					std_logic_vector(11 downto 0)	:= x"5c0";

+--constant	botdr38:					std_logic_vector(11 downto 0)	:= x"5c1";

+

+-- end of ED prefixed opcodes

+

+-- index register instructions

+constant	index4:						std_logic_vector(11 downto 0)	:= x"5d0";

+constant	index5:						std_logic_vector(11 downto 0)	:= x"5d1";

+constant	index6:						std_logic_vector(11 downto 0)	:= x"5d2";

+constant	index7:						std_logic_vector(11 downto 0)	:= x"5d3";

+constant	index8:						std_logic_vector(11 downto 0)	:= x"5d4";

+

+-- alu ops on immediate operand, 7 cycles, 1 m1 cycle

+constant	alui4:						std_logic_vector(11 downto 0)	:= x"5e0";

+constant	alui5:						std_logic_vector(11 downto 0)	:= x"5e1";

+

+-- RST, 11 clock cycles, 1 m1 cycle

+constant	rst4:						std_logic_vector(11 downto 0)	:= x"5f0";

+constant	rst5:						std_logic_vector(11 downto 0)	:= x"5f1";

+constant	rst6:						std_logic_vector(11 downto 0)	:= x"5f2";

+constant	rst7:						std_logic_vector(11 downto 0)	:= x"5f3";

+constant	rst8:						std_logic_vector(11 downto 0)	:= x"5f4";

+

+-- get next opcode byte

+constant	nxtop1:						std_logic_vector(11 downto 0)	:= x"600";

+constant	nxtop2:						std_logic_vector(11 downto 0)	:= x"601";

+

+-- get next operand byte

+constant	nxtoprnd1:					std_logic_vector(11 downto 0)	:= x"610";

+constant	nxtoprnd2:					std_logic_vector(11 downto 0)	:= x"611";

+

+-- general memory read

+constant	genmemrd1:					std_logic_vector(11 downto 0)	:= x"620";

+constant	genmemrd2:					std_logic_vector(11 downto 0)	:= x"621";

+constant	genmemrd3:					std_logic_vector(11 downto 0)	:= x"622";

+

+-- general memory write

+constant	genmemwrt1:					std_logic_vector(11 downto 0)	:= x"630";

+constant	genmemwrt2:					std_logic_vector(11 downto 0)	:= x"631";

+constant	genmemwrt3:					std_logic_vector(11 downto 0)	:= x"632";

+constant	genmemwrt4:					std_logic_vector(11 downto 0)	:= x"633";

+

+-- for 2-byte operands

+constant	obtain_2byte_operand1:		std_logic_vector(11 downto 0)	:= x"640";

+constant	obtain_2byte_operand2:		std_logic_vector(11 downto 0)	:= x"641";

+

+-- for SP increment

+constant	incSP1:						std_logic_vector(11 downto 0)	:= x"650";

+

+-- for SP decrement

+constant	decSP1:						std_logic_vector(11 downto 0)	:= x"660";

+

+-- for handling non-maskable interrupts

+constant	nmi1:						std_logic_vector(11 downto 0)	:= x"670";

+

+-- for handling maskable interrupts

+constant	int1:						std_logic_vector(11 downto 0)	:= x"680";

+

+-- index register bit operations

+constant	index_bit5:					std_logic_vector(11 downto 0)	:= x"690";

+constant	index_bit6:					std_logic_vector(11 downto 0)	:= x"691";

+constant	index_bit7:					std_logic_vector(11 downto 0)	:= x"692";

+

+-- BIT

+constant	index_bit_bit8:				std_logic_vector(11 downto 0)	:= x"6a0";

+

+-- common state for saving index bit operation results other than BIT

+constant	index_save8:				std_logic_vector(11 downto 0)	:= x"6b0";

+

+-- load index register with immediate operand

+constant	ld_index_immediate5:		std_logic_vector(11 downto 0)	:= x"6c0";

+constant	ld_index_immediate6:		std_logic_vector(11 downto 0)	:= x"6c1";

+

+-- add index register to register pair

+constant	add_index_rp5:	   			std_logic_vector(11 downto 0)	:= x"6d0";

+constant	add_index_rp6:  			std_logic_vector(11 downto 0)	:= x"6d1";

+

+-- store index register direct

+constant	st_index_direct5:			std_logic_vector(11 downto 0)	:= x"6e0";

+constant	st_index_direct6:			std_logic_vector(11 downto 0)	:= x"6e1";

+

+-- load index register direct

+constant	ld_index_direct5:			std_logic_vector(11 downto 0)	:= x"6f0";

+constant	ld_index_direct6:			std_logic_vector(11 downto 0)	:= x"6f1";

+constant	ld_index_direct7:			std_logic_vector(11 downto 0)	:= x"6f2";

+constant	ld_index_direct8:			std_logic_vector(11 downto 0)	:= x"6f3";

+constant	ld_index_direct9:			std_logic_vector(11 downto 0)	:= x"6f4";

+constant	ld_index_direct10:			std_logic_vector(11 downto 0)	:= x"6f5";

+constant	ld_index_direct11:			std_logic_vector(11 downto 0)	:= x"6f6";

+constant	ld_index_direct12:			std_logic_vector(11 downto 0)	:= x"6f7";

+constant	ld_index_direct13:			std_logic_vector(11 downto 0)	:= x"6f8";

+constant	ld_index_direct14:			std_logic_vector(11 downto 0)	:= x"6f9";

+

+-- increment or decrement index register

+constant	incdec_index5: 				std_logic_vector(11 downto 0)	:= x"700";

+constant	incdec_index6:				std_logic_vector(11 downto 0)	:= x"701";

+

+-- increment or decrement memory at index register + offset

+constant	incdec_index_memory5: 		std_logic_vector(11 downto 0)	:= x"710";

+constant	incdec_index_memory6:		std_logic_vector(11 downto 0)	:= x"711";

+

+-- load immediate to index register + offset

+constant	ld_index_memory_immed5:		std_logic_vector(11 downto 0)	:= x"720";

+constant	ld_index_memory_immed6:		std_logic_vector(11 downto 0)	:= x"721";

+

+-- store 8 bit register to index register + offset

+constant	st_index_memory5:			std_logic_vector(11 downto 0)	:= x"730";

+

+-- load 8 bit register from index register + offset

+constant	ld_index_memory5:			std_logic_vector(11 downto 0)	:= x"740";

+constant	ld_index_memory6:			std_logic_vector(11 downto 0)	:= x"741";

+constant	ld_index_memory7:			std_logic_vector(11 downto 0)	:= x"742";

+constant	ld_index_memory8:			std_logic_vector(11 downto 0)	:= x"743";

+constant	ld_index_memory9:			std_logic_vector(11 downto 0)	:= x"744";

+constant	ld_index_memory10:			std_logic_vector(11 downto 0)	:= x"745";

+constant	ld_index_memory11:			std_logic_vector(11 downto 0)	:= x"746";

+constant	ld_index_memory12:			std_logic_vector(11 downto 0)	:= x"747";

+constant	ld_index_memory13:			std_logic_vector(11 downto 0)	:= x"748";

+constant	ld_index_memory14:			std_logic_vector(11 downto 0)	:= x"749";

+

+-- 8 bit ALU operations involving memory pointed to by index register	+ offset

+constant	index_alu_ops5:				std_logic_vector(11 downto 0)	:= x"750";

+constant	index_alu_ops6:	 			std_logic_vector(11 downto 0)	:= x"751";

+constant	index_alu_ops7:	 			std_logic_vector(11 downto 0)	:= x"752";

+constant	index_alu_ops8:				std_logic_vector(11 downto 0)	:= x"753";

+constant	index_alu_ops9:				std_logic_vector(11 downto 0)	:= x"754";

+constant	index_alu_ops10:			std_logic_vector(11 downto 0)	:= x"755";

+constant	index_alu_ops11:			std_logic_vector(11 downto 0)	:= x"756";

+constant	index_alu_ops12:			std_logic_vector(11 downto 0)	:= x"757";

+constant	index_alu_ops13:			std_logic_vector(11 downto 0)	:= x"758";

+constant	index_alu_ops14:			std_logic_vector(11 downto 0)	:= x"759";

+

+-- pop index register off stack

+constant	pop_index5:	  				std_logic_vector(11 downto 0)	:= x"770";

+constant	pop_index6:	 				std_logic_vector(11 downto 0)	:= x"771";

+constant	pop_index7:	 				std_logic_vector(11 downto 0)	:= x"772";

+

+-- push index register on stack

+constant	push_index5:	  			std_logic_vector(11 downto 0)	:= x"780";

+constant	push_index6:	 			std_logic_vector(11 downto 0)	:= x"781";

+constant	push_index7:	 			std_logic_vector(11 downto 0)	:= x"782";

+constant	push_index8:				std_logic_vector(11 downto 0)	:= x"783";

+constant	push_index9:				std_logic_vector(11 downto 0)	:= x"784";

+constant	push_index10:				std_logic_vector(11 downto 0)	:= x"785";

+constant	push_index11:				std_logic_vector(11 downto 0)	:= x"786";

+constant	push_index12:				std_logic_vector(11 downto 0)	:= x"787";

+constant	push_index13:				std_logic_vector(11 downto 0)	:= x"788";

+constant	push_index14:				std_logic_vector(11 downto 0)	:= x"789";

+

+-- SPI?

+constant	sp_index5:	  				std_logic_vector(11 downto 0)	:= x"790";

+

+-- XTI?

+constant	xtindex5:	  				std_logic_vector(11 downto 0)	:= x"7a0";

+constant	xtindex6:	 				std_logic_vector(11 downto 0)	:= x"7a1";

+constant	xtindex7:	 				std_logic_vector(11 downto 0)	:= x"7a2";

+constant	xtindex8:					std_logic_vector(11 downto 0)	:= x"7a3";

+constant	xtindex9:					std_logic_vector(11 downto 0)	:= x"7a4";

+constant	xtindex10:					std_logic_vector(11 downto 0)	:= x"7a5";

+constant	xtindex11:					std_logic_vector(11 downto 0)	:= x"7a6";

+constant	xtindex12:					std_logic_vector(11 downto 0)	:= x"7a7";

+constant	xtindex13:					std_logic_vector(11 downto 0)	:= x"7a8";

+constant	xtindex14:					std_logic_vector(11 downto 0)	:= x"7a9";

+

+constant	test:						std_logic_vector(11 downto 0)	:= x"fff";

+constant	waitstate:					std_logic_vector(11 downto 0)	:= x"ffe";

+

+end;
\ No newline at end of file
diff --git a/testsuite/gna/issue30/tb-alu.vhdl b/testsuite/gna/issue30/tb-alu.vhdl
new file mode 100644
index 000000000..a413f9cd2
--- /dev/null
+++ b/testsuite/gna/issue30/tb-alu.vhdl
@@ -0,0 +1,3158 @@
+library	ieee;
+use		ieee.std_logic_1164.all;
+
+package testbench is
+constant	zero:				std_logic_vector(3 downto 0) := x"0";
+constant	one:	   			std_logic_vector(3 downto 0) := x"1";
+constant	two:				std_logic_vector(3 downto 0) := x"2";
+constant	three:	   			std_logic_vector(3 downto 0) := x"3";
+constant	four:				std_logic_vector(3 downto 0) := x"4";
+constant	five:				std_logic_vector(3 downto 0) := x"5";
+constant	six:				std_logic_vector(3 downto 0) := x"6";
+constant	seven:				std_logic_vector(3 downto 0) := x"7";
+constant	eight:				std_logic_vector(3 downto 0) := x"8";
+constant	nine:				std_logic_vector(3 downto 0) := x"9";
+constant	ten:				std_logic_vector(3 downto 0) := x"a";
+constant	eleven:				std_logic_vector(3 downto 0) := x"b";
+constant	twelve:				std_logic_vector(3 downto 0) := x"c";
+constant	thirteen:			std_logic_vector(3 downto 0) := x"d";
+constant	fourteen:			std_logic_vector(3 downto 0) := x"e";
+constant	fifteen:			std_logic_vector(3 downto 0) := x"f";
+
+constant	counter_width:		positive	:= 24;
+
+constant	Disable:			std_logic	:= '0';
+constant	enable:				std_logic	:= '1';
+end;
+
+
+library	ieee;
+use		ieee.std_logic_1164.all;
+use		ieee.std_logic_unsigned.all;
+
+library	work;
+use		work.testbench.all;
+use		work.definitions.all;
+
+entity tb_alu is
+end;
+
+architecture struct_tb_alu of tb_alu is
+component clkgen is
+port(
+	clk_out:	out	std_logic;
+	resetn:		out	std_logic
+);
+end component;
+
+component synchronous_latchN is
+generic(
+	N:	positive
+);
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic_vector((N-1) downto 0);
+	q:				out	std_logic_vector((N-1) downto 0)
+);
+end component;
+
+component synchronous_latch_autoclear is
+port(
+	rstn:			in	std_logic;
+	clock:			in	std_logic;
+	clock_enable:	in	std_logic;
+	d:				in	std_logic;
+	q:				out	std_logic
+);
+end component;
+
+component counterN is
+generic(
+	N:	positive
+);
+port(
+	clock:			in	std_logic;
+	carry_in:		in	std_logic;
+	clock_enable:	in	std_logic;
+	resetn:			in	std_logic;
+	output:			out	std_logic_vector((N-1) downto 0);
+	carry_out:		out	std_logic
+);
+end component;
+
+component alu is
+port(
+	-- control
+	operation:			in	std_logic_vector(4 downto 0);
+
+	-- operands
+	primary_operand:	in	std_logic_vector(7 downto 0);
+	secondary_operand:	in	std_logic_vector(7 downto 0);
+	flags_in:			in	std_logic_vector(7 downto 0);
+
+	--	results
+	output, flags_out:	out	std_logic_vector(7 downto 0);
+	secondary_out:		out	std_logic_vector(7 downto 0)
+);
+end component;
+
+component magnitudeN is
+generic(
+	N:	positive
+);
+port(
+	a, b:	in	std_logic_vector((N-1) downto 0);
+	equal:	out	std_logic;
+	lt:		out	std_logic; 	-- '1' if a < b
+	gt:		out	std_logic	-- '1' if a > b
+);
+end component;
+
+
+signal	clock: 						std_logic;
+signal	resetn:						std_logic;
+
+signal	notclock:					std_logic;
+
+signal	next_state:					std_logic_vector(3 downto 0);
+signal	nxt_state:					std_logic_vector(3 downto 0);
+signal	current_state:				std_logic_vector(3 downto 0);
+
+signal	counter_state:				std_logic;
+signal	counter_clock:				std_logic;
+signal	counter_clock_enable:		std_logic;
+signal	counter_out:				std_logic_vector((counter_width - 1) downto 0);
+signal	counter_zero:				std_logic;
+
+signal	zero_secondary_alu_result:	std_logic;
+
+signal	test_bits:					std_logic;
+signal	res_bits:					std_logic;
+signal	res_result:					std_logic_vector(7 downto 0);
+
+signal	alu_result:					std_logic_vector(7 downto 0);
+signal	secondary_alu_result:		std_logic_vector(7 downto 0);
+signal	flags_in:					std_logic_vector(7 downto 0);
+signal	flags:						std_logic_vector(7 downto 0);
+
+signal	sum_check:					std_logic_vector(8 downto 0);
+signal	sum_overflow_check:			std_logic;
+signal	sum_zero_check:				std_logic;
+signal	half_sum_check:				std_logic_vector(4 downto 0);
+signal	sum_checker:				std_logic;
+
+signal	subtract_check:				std_logic_vector(8 downto 0);
+signal	subtract_overflow_check:	std_logic;
+signal	subtract_zero_check:		std_logic;
+signal	half_difference_check:		std_logic_vector(4 downto 0);
+signal	subtract_checker:			std_logic;
+
+signal	and_check:					std_logic_vector(7 downto 0);
+signal	and_zero_check:				std_logic;
+signal	and_parity_check:			std_logic;
+signal	and_checker:				std_logic;
+
+signal	xor_check:					std_logic_vector(7 downto 0);
+signal	xor_zero_check:				std_logic;
+signal	xor_parity_check:			std_logic;
+signal	xor_checker:				std_logic;
+
+signal	or_check:					std_logic_vector(7 downto 0);
+signal	or_zero_check:				std_logic;
+signal	or_parity_check:			std_logic;
+signal	or_checker:					std_logic;
+
+signal	rlc_check:					std_logic_vector(7 downto 0);
+signal	rlc_zero_check:				std_logic;
+signal	rlc_parity_check:			std_logic;
+signal	rlc_checker:				std_logic;
+
+signal	rrc_check:					std_logic_vector(7 downto 0);
+signal	rrc_zero_check:				std_logic;
+signal	rrc_parity_check:			std_logic;
+signal	rrc_checker:				std_logic;
+
+signal	rl_check:					std_logic_vector(7 downto 0);
+signal	rl_zero_check:				std_logic;
+signal	rl_parity_check:			std_logic;
+signal	rl_checker:					std_logic;
+
+signal	rr_check:					std_logic_vector(7 downto 0);
+signal	rr_zero_check:				std_logic;
+signal	rr_parity_check:			std_logic;
+signal	rr_checker:					std_logic;
+
+signal	daa_unimp:					std_logic;
+
+signal	cpl_check:					std_logic_vector(7 downto 0);
+signal	cpl_checker:				std_logic;
+
+signal	scf_checker:				std_logic;
+
+signal	ccf_flags:					std_logic_vector(7 downto 0);
+
+signal	sla_check:					std_logic_vector(7 downto 0);
+signal	sla_zero_check:				std_logic;
+signal	sla_parity_check:			std_logic;
+signal	sla_checker:				std_logic;
+
+signal	sra_check:					std_logic_vector(7 downto 0);
+signal	sra_zero_check:				std_logic;
+signal	sra_parity_check:			std_logic;
+signal	sra_checker:				std_logic;
+
+signal	sll_check:					std_logic_vector(7 downto 0);
+signal	sll_zero_check:				std_logic;
+signal	sll_parity_check:			std_logic;
+signal	sll_checker:				std_logic;
+
+signal	srl_check:					std_logic_vector(7 downto 0);
+signal	srl_zero_check:				std_logic;
+signal	srl_parity_check:			std_logic;
+signal	srl_checker:				std_logic;
+
+signal	bit_checker:				std_logic;
+signal	bit_check:					std_logic_vector(7 downto 0);
+signal	bit_zero_checker:			std_logic;
+signal	res_checker:				std_logic;
+signal	set_checker:				std_logic;
+
+signal	inrc_zero:					std_logic;
+signal	inrc_parity:				std_logic;
+
+signal	primary_rld_check:			std_logic_vector(7 downto 0);
+signal	secondary_rld_check:		std_logic_vector(7 downto 0);
+signal	rld_zero_check:				std_logic;
+signal	rld_parity_check:			std_logic;
+signal	primary_rld_checker:		std_logic;
+signal	secondary_rld_checker:		std_logic;
+
+signal	primary_rrd_check:			std_logic_vector(7 downto 0);
+signal	secondary_rrd_check:		std_logic_vector(7 downto 0);
+signal	rrd_zero_check:				std_logic;
+signal	rrd_parity_check:			std_logic;
+signal	primary_rrd_checker:		std_logic;
+signal	secondary_rrd_checker:		std_logic;
+
+signal	bmtc_check:					std_logic_vector(7 downto 0);
+signal	bmtc_parity_check:			std_logic;
+signal	bmtc_checker:				std_logic;
+
+signal	done:						std_logic;
+
+begin
+	u1: clkgen port map(
+			clk_out => clock,
+			resetn => resetn
+		);
+
+	notclock <= not clock;
+
+	u2: synchronous_latchN
+			generic map(
+				N => 4
+			)
+			port map(
+				rstn => resetn,
+				clock => notclock,
+				clock_enable => '1',
+				d => next_state,
+				q => nxt_state
+			);
+
+	u3: synchronous_latchN
+			generic map(
+				N => 4
+			)
+			port map(
+				rstn => resetn,
+				clock => clock,
+				clock_enable => '1',
+				d => nxt_state,
+				q => current_state
+			);
+
+	u4: synchronous_latch_autoclear port map(
+			rstn => resetn,
+			clock => notclock,
+			clock_enable => counter_clock,
+			d => counter_state,
+			q => counter_clock_enable
+		);
+
+	u5: counterN
+			generic map(
+				N => counter_width
+			)
+			port map(
+				clock => clock,
+				carry_in => '1',
+				clock_enable => counter_clock_enable,
+				resetn => resetn,
+				output => counter_out((counter_width - 1) downto 0),
+				carry_out => open
+			);
+
+	u6: alu port map(
+			operation => counter_out(21 downto 17),
+			primary_operand => counter_out(7 downto 0),
+			secondary_operand => counter_out(15 downto 8),
+			flags_in => flags_in,
+			output => alu_result,
+			flags_out => flags,
+			secondary_out => secondary_alu_result
+		);
+
+	flags_in <= (	carry_bit => counter_out(16),
+					others => '0');
+
+	u7: magnitudeN
+			generic map(
+				N => counter_width
+			)
+			port map(
+				a => counter_out,
+				b => x"000000",
+				equal => counter_zero,
+				lt => open,
+				gt => open
+			);
+
+	u8: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => sum_check(7 downto 0),
+				equal => sum_checker,
+				lt => open,
+				gt => open
+			);
+
+	u9: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => secondary_alu_result,
+				b => x"00",
+				equal => zero_secondary_alu_result,
+				lt => open,
+				gt => open
+			);
+	u10: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => subtract_check(7 downto 0),
+				equal => subtract_checker,
+				lt => open,
+				gt => open
+			);
+
+	u11: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => and_check(7 downto 0),
+				equal => and_checker,
+				lt => open,
+				gt => open
+			);
+
+	u12: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => xor_check(7 downto 0),
+				equal => xor_checker,
+				lt => open,
+				gt => open
+			);
+
+	u13: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => or_check(7 downto 0),
+				equal => or_checker,
+				lt => open,
+				gt => open
+			);
+
+	u14: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => rlc_check(7 downto 0),
+				equal => rlc_checker,
+				lt => open,
+				gt => open
+			);
+
+	u15: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => rrc_check(7 downto 0),
+				equal => rrc_checker,
+				lt => open,
+				gt => open
+			);
+
+	u16: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => rl_check(7 downto 0),
+				equal => rl_checker,
+				lt => open,
+				gt => open
+			);
+
+	u17: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => rr_check(7 downto 0),
+				equal => rr_checker,
+				lt => open,
+				gt => open
+			);
+
+	u18: magnitudeN
+			generic map(
+				N => 17
+			)
+			port map(
+				a => counter_out(16 downto 0),
+				b => "00000000000000000",
+				equal => daa_unimp,
+				lt => open,
+				gt => open
+			);
+
+	u19: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => cpl_check(7 downto 0),
+				equal => cpl_checker,
+				lt => open,
+				gt => open
+			);
+
+	u20: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => counter_out(7 downto 0),
+				equal => scf_checker,
+				lt => open,
+				gt => open
+			);
+
+	u21: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => sla_check(7 downto 0),
+				equal => sla_checker,
+				lt => open,
+				gt => open
+			);
+
+
+	u22: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => sra_check(7 downto 0),
+				equal => sra_checker,
+				lt => open,
+				gt => open
+			);
+
+	u23: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => sll_check(7 downto 0),
+				equal => sll_checker,
+				lt => open,
+				gt => open
+			);
+
+	u24: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => srl_check(7 downto 0),
+				equal => srl_checker,
+				lt => open,
+				gt => open
+			);
+
+	u25: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => counter_out(15 downto 8),
+				equal => bit_checker,
+				lt => open,
+				gt => open
+			);
+
+	bit_check <= (counter_out(7 downto 0) and counter_out(15 downto 8));
+
+	u26: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => x"00",
+				b => bit_check,
+				equal => bit_zero_checker,
+				lt => open,
+				gt => open
+			);
+
+	u27: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => res_result,
+				equal => res_checker,
+				lt => open,
+				gt => open
+			);
+
+	u28: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => primary_rld_check,
+				equal => primary_rld_checker,
+				lt => open,
+				gt => open
+			);
+
+	u29: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => secondary_alu_result,
+				b => secondary_rld_check,
+				equal => secondary_rld_checker,
+				lt => open,
+				gt => open
+			);
+
+	u30: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => primary_rrd_check,
+				equal => primary_rrd_checker,
+				lt => open,
+				gt => open
+			);
+
+	u31: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => secondary_alu_result,
+				b => secondary_rrd_check,
+				equal => secondary_rrd_checker,
+				lt => open,
+				gt => open
+			);
+
+	u32: magnitudeN
+			generic map(
+				N => 8
+			)
+			port map(
+				a => alu_result,
+				b => bmtc_check,
+				equal => bmtc_checker,
+				lt => open,
+				gt => open
+			);
+
+	u33: magnitudeN
+			generic map(
+				N => 22
+			)
+			port map(
+				a => counter_out(21 downto 0),
+				b => (others => '1'), -- x"3fffff",
+				equal => done,
+				lt => open,
+				gt => open
+			);
+
+	process(current_state, resetn) begin
+		if resetn = '0' then
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+			next_state <= zero;
+		else
+			case current_state is
+				when zero =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= one;
+
+				when one =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					assert counter_zero = '1'
+					report "counter initialisation failure"
+					severity failure;
+
+					next_state <= two;
+
+				when two =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= three;
+
+				when three =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					case counter_out(21 downto 17) is
+						when add_operation | adc_operation =>
+							assert sum_checker = '1'
+							report "incorrect sum"
+							severity failure;
+
+							assert sum_check(8) = flags(carry_bit)
+							report "incorrect addition carry flag"
+							severity failure;
+
+							assert sum_overflow_check = flags(parity_overflow_bit)
+							report "incorrect addition overflow flag"
+							severity failure;
+
+							assert sum_zero_check = flags(zero_bit)
+							report "incorrect addition zero flag"
+							severity failure;
+
+							assert half_sum_check(4) = flags(half_carry_bit)
+							report "incorrect interdigit carry flag"
+							severity failure;
+
+		                    assert alu_result(7) = flags(sign_bit)
+        		            report "incorrect addition sign flag"
+                    		severity failure;
+
+							assert flags(add_sub_bit) = '0'
+							report "incorrect addition add/subtract flag"
+							severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for add/adc"
+							severity failure;
+
+                        when sub_operation | sbc_operation =>
+                        	assert subtract_checker = '1'
+							report "incorrect difference"
+							severity failure;
+
+							assert subtract_check(8) = flags(carry_bit)
+							report "incorrect subtraction borrow flag"
+							severity failure;
+
+							assert subtract_overflow_check = flags(parity_overflow_bit)
+							report "incorrect subtraction overflow flag"
+							severity failure;
+
+							assert subtract_zero_check = flags(zero_bit)
+							report "incorrect subtraction zero flag"
+							severity failure;
+
+							assert half_difference_check(4) = flags(half_carry_bit)
+							report "incorrect interdigit borrow flag"
+							severity failure;
+
+		                    assert alu_result(7) = flags(sign_bit)
+		                    report "incorrect subtraction sign flag"
+		                    severity failure;
+
+							assert flags(add_sub_bit) = '1'
+							report "incorrect subtraction add/subtract flag"
+							severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for sub/sbc"
+							severity failure;
+
+                        when and_operation =>
+							assert and_checker = '1'
+							report "incorrect logical AND result"
+							severity failure;
+
+							assert and_zero_check = flags(zero_bit)
+							report "incorrect logical AND zero flag"
+							severity failure;
+
+							assert and_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for logical AND"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for logical AND"
+            		        severity failure;
+
+                    		assert flags(half_carry_bit) = '1'
+		                    report "incorrect half-carry flag for logical AND"
+        		            severity failure;
+
+                		    assert flags(add_sub_bit) = '0'
+		                    report "incorrect add/subtract bit for logical AND"
+        		            severity failure;
+
+                		    assert flags(carry_bit) = '0'
+		                    report "incorrect carry bit for logical AND"
+        		            severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for and"
+							severity failure;
+
+						when xor_operation =>
+							assert xor_checker = '1'
+							report "incorrect logical XOR result"
+							severity failure;
+
+							assert xor_zero_check = flags(zero_bit)
+							report "incorrect logical XOR zero flag"
+							severity failure;
+
+							assert xor_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for logical XOR"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for logical XOR"
+        		            severity failure;
+
+                		    assert flags(half_carry_bit) = '1'
+		                    report "incorrect half-carry flag for logical XOR"
+        		            severity failure;
+
+                		    assert flags(add_sub_bit) = '0'
+		                    report "incorrect add/subtract flag for logical XOR"
+		                    severity failure;
+
+        		            assert flags(carry_bit) = '0'
+                		    report "incorrect carry bit for logical XOR"
+		                    severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for xor"
+							severity failure;
+
+						when or_operation =>
+							assert or_checker = '1'
+							report "incorrect logical OR result"
+							severity failure;
+
+							assert or_zero_check = flags(zero_bit)
+							report "incorrect logical OR zero flag"
+							severity failure;
+
+							assert or_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for logical OR"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for logical OR"
+        		            severity failure;
+
+		                    assert flags(half_carry_bit) = '1'
+		                    report "incorrect half-carry flag for logical OR"
+        		            severity failure;
+
+                		    assert flags(add_sub_bit) = '0'
+		                    report "incorrect add/subtract flag for logical OR"
+		                    severity failure;
+
+        		            assert flags(carry_bit) = '0'
+		                    report "incorrect carry flag for logical OR"
+		                    severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for OR operation"
+							severity failure;
+
+						when cmp_operation =>
+							assert subtract_checker = '1'
+							report "incorrect compare result"
+							severity failure;
+
+							assert subtract_check(8) = flags(carry_bit)
+							report "incorrect compare borrow flag"
+							severity failure;
+
+							assert subtract_overflow_check = flags(parity_overflow_bit)
+							report "incorrect compare overflow flag"
+							severity failure;
+
+							assert subtract_zero_check = flags(zero_bit)
+							report "incorrect compare zero flag"
+							severity failure;
+
+							assert half_difference_check(4) = flags(half_carry_bit)
+							report "incorrect compare interdigit borrow flag"
+							severity failure;
+
+		                    assert alu_result(7) = flags(sign_bit)
+		                    report "incorrect compare sign flag"
+		                    severity failure;
+
+							assert flags(add_sub_bit) = '1'
+							report "incorrect compare add/subtract flag"
+							severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for compare"
+							severity failure;
+
+						when rlc_operation =>
+							assert rlc_checker = '1'
+							report "incorrect rlc result"
+							severity failure;
+
+							assert rlc_zero_check = flags(zero_bit)
+							report "incorrect rlc zero flag"
+							severity failure;
+
+							assert rlc_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for rlc"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for rlc"
+                		    severity failure;
+
+		                    assert flags(half_carry_bit) = '0'
+        		            report "incorrect half-carry flag for rlc"
+                    		severity failure;
+
+		                    assert flags(add_sub_bit) = '0'
+        		            report "incorrect add/subtract flag for rlc"
+                		    severity failure;
+
+		                    assert flags(carry_bit) = counter_out(7)
+        		            report "incorrect carry flag for rlc"
+                		    severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for rls"
+							severity failure;
+
+						when rrc_operation =>
+							assert rrc_checker = '1'
+							report "incorrect rrc result"
+							severity failure;
+
+							assert rrc_zero_check = flags(zero_bit)
+							report "incorrect rrc zero bit"
+							severity failure;
+
+							assert rrc_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for rrc"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for rrc"
+		                    severity failure;
+
+		                    assert flags(half_carry_bit) = '0'
+        		            report "incorrect half-carry flag for rrc"
+                		    severity failure;
+
+		                    assert flags(add_sub_bit) = '0'
+        		            report "incorrect add/subtract flag for rrc"
+                		    severity failure;
+
+		                    assert flags(carry_bit) = counter_out(0)
+        		            report "incorrect carry flag for rrc"
+                		    severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for rrc"
+							severity failure;
+
+						when rl_operation =>
+							assert rl_checker = '1'
+							report "incorrect rl result"
+							severity failure;
+
+							assert rl_zero_check = flags(zero_bit)
+							report "incorrect rl zero bit"
+							severity failure;
+
+							assert rl_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for rl"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for rl"
+                		    severity failure;
+
+		                    assert flags(half_carry_bit) = '0'
+        		            report "incorrect half-carry flag for rl"
+                		    severity failure;
+
+		                    assert flags(add_sub_bit) = '0'
+		                    report "incorrect add/subtract flag for rl"
+        		            severity failure;
+
+		                    assert flags(carry_bit) = counter_out(7)
+		                    report "incorrect carry flag for rl"
+        		            severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for rl"
+							severity failure;
+
+                		when rr_operation =>
+                			assert rr_checker = '1'
+							report "incorrect rr result"
+							severity failure;
+
+							assert rr_zero_check = flags(zero_bit)
+							report "incorrect rr zero bit"
+							severity failure;
+
+							assert rr_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for rr"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for rr"
+                		    severity failure;
+
+		                    assert flags(half_carry_bit) = '0'
+        		            report "incorrect half-carry flag for rr"
+                		    severity failure;
+
+		                    assert flags(add_sub_bit) = '0'
+        		            report "incorrect add/subtract flag for rr"
+                		    severity failure;
+
+		                    assert flags(carry_bit) = counter_out(0)
+        		            report "incorrect carry flag for rr"
+                		    severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for rr"
+							severity failure;
+
+						when daa_operation =>
+							assert daa_unimp = '0'
+							report "DAA is not implemented"
+							severity note;
+
+						when cpl_operation =>
+							assert cpl_checker = '1'
+							report "incorrect cpl result"
+							severity failure;
+
+							assert flags(add_sub_bit) = '1'
+							report "incorrect cpl add/sub flag"
+							severity failure;
+
+							assert flags(half_carry_bit) = '1'
+							report "incorrect cpl half-carry flag"
+							severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for cpl"
+							severity failure;
+
+						when scf_operation =>
+							assert scf_checker = '1'
+							report "incorrect scf result"
+							severity failure;
+
+							assert flags(carry_bit) = '1'
+							report "incorrect carry flag for scf"
+							severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for scf"
+							severity failure;
+
+						when ccf_operation =>
+							assert scf_checker = '1'
+							report "incorrect ccf result"
+							severity failure;
+
+							assert flags(carry_bit) = not (counter_out(16))
+							report "incorrect ccf carry flag"
+							severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for ccf"
+							severity failure;
+
+                		when sla_operation =>
+                			assert sla_checker = '1'
+							report "incorrect sla result"
+							severity failure;
+
+							assert sla_zero_check = flags(zero_bit)
+							report "incorrect sla zero flag"
+							severity failure;
+
+							assert sla_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for sla"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for sla"
+        		            severity failure;
+
+                		    assert flags(half_carry_bit) = '0'
+		                    report "incorrect half-carry flag for sla"
+        		            severity failure;
+
+                		    assert flags(add_sub_bit) = '0'
+		                    report "incorrect add/subtract flag for sla"
+        		            severity failure;
+
+                		    assert flags(carry_bit) = counter_out(7)
+		                    report "incorrect carry bit for flag"
+        		            severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for sla"
+							severity failure;
+
+                        when sra_operation =>
+                        	assert sra_checker = '1'
+                        	report "incorrect sra result"
+							severity failure;
+
+							assert sra_zero_check = flags(zero_bit)
+							report "incorrect sra zero flag"
+							severity failure;
+
+							assert sra_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for sra"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for sra"
+        		            severity failure;
+
+                		    assert flags(half_carry_bit) = '0'
+		                    report "incorrect half-carry flag for sra"
+        		            severity failure;
+
+                		    assert flags(add_sub_bit) = '0'
+		                    report "incorrect add/subtract flag for sra"
+		                    severity failure;
+
+        		            assert flags(carry_bit) = counter_out(0)
+		                    report "incorrect carry flag for sra"
+        		            severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for sra"
+							severity failure;
+
+						when sll_operation =>
+							assert sll_checker = '1'
+							report "incorrect sll result"
+							severity failure;
+
+							assert sll_zero_check = flags(zero_bit)
+							report "incorrect sll zero flag"
+							severity failure;
+
+							assert sll_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for sll"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for sll"
+		                    severity failure;
+
+		                    assert flags(half_carry_bit) = '0'
+        		            report "incorrect half-carry flag for sll"
+		                    severity failure;
+
+        		            assert flags(add_sub_bit) = '0'
+		                    report "incorrect add/subtract flag for sll"
+        		            severity failure;
+
+                		    assert flags(carry_bit) = counter_out(7)
+		                    report "incorrect carry flag for sll"
+		                    severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for sll"
+							severity failure;
+
+        				when srl_operation =>
+        					assert srl_checker = '1'
+							report "incorrect srl result"
+							severity failure;
+
+							assert srl_zero_check = flags(zero_bit)
+							report "incorrect srl zero flag"
+							severity failure;
+
+							assert srl_parity_check = flags(parity_overflow_bit)
+							report "incorrect parity flag for srl"
+							severity failure;
+
+							assert alu_result(7) = flags(sign_bit)
+							report "incorrect sign flag for srl"
+                		    severity failure;
+
+		                    assert flags(half_carry_bit) = '0'
+        		            report "incorrect half-carry flag for srl"
+                		    severity failure;
+
+		                    assert flags(add_sub_bit) = '0'
+        		            report "incorrect add/subtract flag for srl"
+                		    severity failure;
+
+		                    assert flags(carry_bit) = counter_out(0)
+        		            report "incorrect carry flag for srl"
+                		    severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for srl"
+							severity failure;
+
+						when bit_operation =>
+							assert bit_checker = '1'
+							report "incorrect result for bit operation"
+							severity failure;
+
+							if test_bits = '1' then
+								if bit_zero_checker = '1' then
+									assert flags(zero_bit) = '1'
+									report "BIT: zero flag != '1'"
+									severity failure;
+								elsif bit_zero_checker = '0' then
+									assert flags(zero_bit) = '0'
+									report "BIT: zero flag != '0'"
+									severity failure;
+								end if;
+							end if;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for bit"
+							severity failure;
+
+						when res_operation =>
+							if test_bits = '1' then
+								assert res_checker = '1'
+								report "incorrect result for RES"
+								severity failure;
+							end if;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for res"
+							severity failure;
+
+						when set_operation =>
+							if test_bits = '1' then
+								assert or_checker = '1'
+								report "incorrect result for SET"
+								severity failure;
+							end if;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for set"
+							severity failure;
+
+						when in16_operation =>
+							assert scf_checker = '1'
+							report "incorrect result for in r,(C)"
+							severity failure;
+
+							assert flags(zero_bit) = inrc_zero
+							report "incorrect zero flag for in r,(c)"
+							severity failure;
+
+							assert flags(parity_overflow_bit) = inrc_parity
+							report "incorrect parity flag for in r,(c)"
+							severity failure;
+
+							assert flags(half_carry_bit) = '0'
+							report "incorrect half-carry flag for in r,(c)"
+							severity failure;
+
+							assert flags(add_sub_bit) = '0'
+							report "incorrect add/subtract flag for in r,(c)"
+							severity failure;
+
+							assert flags(sign_bit) = alu_result(sign_bit)
+							report "incorrect sign flag for in r,(c)"
+							severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for in r, (c)"
+							severity failure;
+
+						when rld_operation =>
+							assert primary_rld_checker = '1'
+							report "incorrect primary result for rld"
+							severity failure;
+
+							assert secondary_rld_checker = '1'
+							report "incorrect secondary rld result"
+							severity failure;
+
+							assert alu_result(sign_bit) = flags(sign_bit)
+							report "incorrect sign flag for rld"
+							severity failure;
+
+                            assert rld_zero_check = flags(zero_bit)
+                            report "incorrect zero flag for rld"
+                            severity failure;
+
+                            assert rld_parity_check = flags(parity_overflow_bit)
+                            report "incorrect parity flag for rld"
+                            severity failure;
+
+                            assert flags(half_carry_bit) = '0'
+                            report "incorrect half-carry flag for rld"
+                            severity failure;
+
+                            assert flags(add_sub_bit) = '0'
+                            report "incorrect add/subtract flag for rld"
+                            severity failure;
+
+						when rrd_operation =>
+							assert primary_rrd_checker = '1'
+							report "incorrect primary result for rrd"
+							severity failure;
+
+							assert secondary_rrd_checker = '1'
+							report "incorrect secondary rrd result"
+							severity failure;
+
+							assert alu_result(sign_bit) = flags(sign_bit)
+							report "incorrect sign flag for rrd"
+							severity failure;
+
+                            assert rrd_zero_check = flags(zero_bit)
+                            report "incorrect zero flag for rrd"
+                            severity failure;
+
+                            assert rrd_parity_check = flags(parity_overflow_bit)
+                            report "incorrect parity flag for rrd"
+                            severity failure;
+
+                            assert flags(half_carry_bit) = '0'
+                            report "incorrect half-carry flag for rrd"
+                            severity failure;
+
+                            assert flags(add_sub_bit) = '0'
+                            report "incorrect add/subtract flag for rrd"
+                            severity failure;
+
+						when blockterm16_operation =>
+							assert bmtc_checker = '1'
+							report "incorrect bmtc result"
+							severity failure;
+
+							assert bmtc_parity_check = flags(parity_overflow_bit)
+							report "incorrect bmtc parity bit"
+							severity failure;
+
+							assert zero_secondary_alu_result = '1'
+							report "secondary_alu_result != 0 for block termination"
+							severity failure;
+
+						when others =>
+--							assert counter_out(16 downto 0) /= ('0' & x"0000")
+--							report "unimplemented alu operation"
+--							severity warning;
+
+					end case;
+
+					if done = '1' then
+						counter_state <= Disable;
+						counter_clock <= Disable;
+						next_state <= fifteen;
+					else
+						counter_clock <= enable;
+						counter_state <= enable;
+						next_state <= two;
+					end if;
+
+				when four =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= five;
+
+				when five =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= six;
+
+				when six =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= seven;
+
+				when seven =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+
+					next_state <= eight;
+
+				when eight =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= nine;
+
+				when nine =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= ten;
+
+				when ten =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= eleven;
+
+				when eleven =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= twelve;
+
+				when twelve =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= thirteen;
+
+				when thirteen =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+
+					next_state <= fourteen;
+
+				when fourteen =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= fifteen;
+
+				when fifteen =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					assert false
+					report "test success"
+					severity note;
+
+				when others =>
+-- default states begin here
+counter_state <= Disable;
+counter_clock <= Disable;
+
+test_bits <=	(
+				((		counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(		counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(		counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0))) or
+				((not	counter_out(7))	and	(not	counter_out(6))	and	(not	counter_out(5))	and	(not	counter_out(4))	and	(not	counter_out(3))	and	(not	counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0)))
+				);
+
+res_bits <=		(
+				((not	counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(not	counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (not	counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(not	counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(not	counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(not	counter_out(2))	and	(		counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(not	counter_out(1))	and	(		counter_out(0))) or
+				((		counter_out(7))	and	(		counter_out(6))	and (		counter_out(5))	and	(		counter_out(4))	and	(		counter_out(3))	and	(		counter_out(2))	and	(		counter_out(1))	and	(not	counter_out(0)))
+				);
+
+sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
+sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
+sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
+half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
+
+subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
+subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
+half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
+
+and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
+and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
+and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
+
+xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
+xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
+xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
+
+or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
+or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
+or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
+
+rlc_check <= counter_out(6 downto 0) & counter_out(7);
+rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
+rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
+
+rrc_check <= counter_out(0) & counter_out(7 downto 1);
+rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
+rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
+
+rl_check <= counter_out(6 downto 0) & counter_out(16);
+rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
+rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
+
+rr_check <= counter_out(16) & counter_out(7 downto 1);
+rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
+rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
+
+cpl_check <= not counter_out(7 downto 0);
+
+sla_check <= counter_out(6 downto 0) & '0';
+sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
+sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
+
+sra_check <= counter_out(7) & counter_out(7 downto 1);
+sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
+sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
+
+sll_check <= counter_out(6 downto 0) & '0';
+sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
+sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
+
+srl_check <= '0' & counter_out(7 downto 1);
+srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
+srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
+
+inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
+inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
+
+primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
+secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
+rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
+rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
+
+primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
+secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
+rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
+rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
+
+bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
+bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
+-- default states end here
+
+					next_state <= zero;
+					assert false
+					report "state machine failure"
+					severity failure;
+
+			end case;
+		end if;
+	end process;
+end;
diff --git a/testsuite/gna/issue30/testsuite.sh b/testsuite/gna/issue30/testsuite.sh
new file mode 100755
index 000000000..39db46a30
--- /dev/null
+++ b/testsuite/gna/issue30/testsuite.sh
@@ -0,0 +1,15 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_FLAGS=--ieee=synopsys
+analyze definitions.vhdl
+analyze alu.vhdl
+analyze basicblocks.vhdl
+analyze tb-alu.vhdl
+elab_simulate tb_alu --stop-time=50ns
+
+clean
+
+echo "Test successful"
+