Add testcase for #663

3 files changed, 90 insertions, 0 deletions

diff --git a/testsuite/gna/issue663/ent.vhdl b/testsuite/gna/issue663/ent.vhdl
new file mode 100644
index 000000000..81254d5b4
--- /dev/null
+++ b/testsuite/gna/issue663/ent.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+end entity ent;
+
+architecture a of ent is
+  signal clk : std_logic := '0';
+
+  signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000";
+  alias check_stable_start_event_1  : std_logic is check_stable_in_1(1);
+  alias check_stable_end_event_1    : std_logic is check_stable_in_1(2);
+  alias check_stable_expr_1         : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5);
+
+  signal check_stable_en_1 : std_logic;
+
+  signal en, start_event, end_event, expr : std_logic := '1';
+
+  procedure check_stable(
+    signal clock               : in std_logic;
+    signal en                  : in std_logic;
+    signal start_event         : in std_logic;
+    signal end_event           : in std_logic;
+    signal expr                : in std_logic_vector) is
+  begin
+    wait until (falling_edge(clock) or rising_edge(clock)) and (to_x01(en) = '1');
+  end;
+
+begin
+  clock : process is
+  begin
+    clk <= '1', '0' after 5 ns;
+    wait;
+  end process clock;
+
+  check_stable_1 : check_stable(clk,
+                                check_stable_en_1,
+                                check_stable_start_event_1,
+                                check_stable_end_event_1,
+                                check_stable_expr_1);
+
+end architecture;
diff --git a/testsuite/gna/issue663/repro.vhdl b/testsuite/gna/issue663/repro.vhdl
new file mode 100644
index 000000000..220c4820f
--- /dev/null
+++ b/testsuite/gna/issue663/repro.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+end entity repro;
+
+architecture a of repro is
+  signal clk : std_logic := '0';
+
+  signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000";
+  alias check_stable_expr_1         : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5);
+
+  procedure check_stable(
+    signal clock               : in std_logic;
+    signal expr                : in std_logic_vector) is
+  begin
+    wait until rising_edge(clock);
+  end;
+
+begin
+  clock : process is
+  begin
+    clk <= '1', '0' after 5 ns;
+    wait;
+  end process clock;
+
+--  process
+--  begin
+--    check_stable(clk, check_stable_expr_1);
+--    wait on clk, check_stable_expr_1;
+--    assert check_stable_expr_1 = "000";
+--  end process;
+  check_stable_1 : check_stable(clk, check_stable_expr_1);
+
+end architecture;
diff --git a/testsuite/gna/issue663/testsuite.sh b/testsuite/gna/issue663/testsuite.sh
new file mode 100755
index 000000000..e25f60643
--- /dev/null
+++ b/testsuite/gna/issue663/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze ent.vhdl
+elab_simulate ent
+
+analyze repro.vhdl
+elab_simulate repro
+
+clean
+
+echo "Test successful"