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author | Tristan Gingold <tgingold@free.fr> | 2023-02-07 15:19:27 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:04:33 +0100 |
commit | 410f08aa700ee3c4cee834de2266ee9a09fd27bf (patch) | |
tree | 65258c4bf3c2a4cb292c8b63526e28aad188b24f /testsuite/gna | |
parent | c348e697dd910173d6d64dc78b43adad316e892a (diff) | |
download | ghdl-410f08aa700ee3c4cee834de2266ee9a09fd27bf.tar.gz ghdl-410f08aa700ee3c4cee834de2266ee9a09fd27bf.tar.bz2 ghdl-410f08aa700ee3c4cee834de2266ee9a09fd27bf.zip |
testsuite/gna: add a reproducer for #2344
Diffstat (limited to 'testsuite/gna')
-rw-r--r-- | testsuite/gna/issue2344/ent1.vhdl | 36 | ||||
-rwxr-xr-x | testsuite/gna/issue2344/testsuite.sh | 11 |
2 files changed, 47 insertions, 0 deletions
diff --git a/testsuite/gna/issue2344/ent1.vhdl b/testsuite/gna/issue2344/ent1.vhdl new file mode 100644 index 000000000..63099cbb9 --- /dev/null +++ b/testsuite/gna/issue2344/ent1.vhdl @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent1 is +end entity; + +architecture a of ent1 is + signal s1 : std_ulogic_vector(2 downto 0); + signal s2 : std_ulogic; + + procedure proc ( + signal a : in std_ulogic_vector(2 downto 0) + ) is + variable b : std_ulogic; + begin + if s2 = '0' then + b := a(0); + end if; + end procedure; + +begin + process (all) is + begin + proc(a => s1); + end process; +end architecture; + +library ieee; + +entity ent2 is +end entity; + +architecture a of ent2 is +begin + ent1: entity work.ent1; +end a; diff --git a/testsuite/gna/issue2344/testsuite.sh b/testsuite/gna/issue2344/testsuite.sh new file mode 100755 index 000000000..e90fa5c69 --- /dev/null +++ b/testsuite/gna/issue2344/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze ent1.vhdl +elab_simulate ent2 + +clean + +echo "Test successful" |