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authorTristan Gingold <tgingold@free.fr>2019-11-25 06:54:56 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-25 06:54:56 +0100
commit2733fd6535cfd10c64ff8383bc1df890faaf076c (patch)
treed010288f4fb962247e683111fadfcd1e3b58ffc1 /testsuite/gna
parent8a2bd07c3f7a3f99aa3cf0017dbba69df28aa1b9 (diff)
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testsuite: add a reproducer for #265
Diffstat (limited to 'testsuite/gna')
-rw-r--r--testsuite/gna/issue265/ex1_entity.vhdl12
-rw-r--r--testsuite/gna/issue265/ex1_top.vhdl32
-rwxr-xr-xtestsuite/gna/issue265/testsuite.sh10
3 files changed, 54 insertions, 0 deletions
diff --git a/testsuite/gna/issue265/ex1_entity.vhdl b/testsuite/gna/issue265/ex1_entity.vhdl
new file mode 100644
index 000000000..fef4f6eaf
--- /dev/null
+++ b/testsuite/gna/issue265/ex1_entity.vhdl
@@ -0,0 +1,12 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ex1_entity is
+ port (
+ X : inout std_logic
+ );
+end entity;
+
+architecture a of ex1_entity is
+begin
+end architecture;
diff --git a/testsuite/gna/issue265/ex1_top.vhdl b/testsuite/gna/issue265/ex1_top.vhdl
new file mode 100644
index 000000000..3771353ba
--- /dev/null
+++ b/testsuite/gna/issue265/ex1_top.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ex1_top is
+end entity;
+
+architecture a of ex1_top is
+ signal A : boolean;
+
+ function conv_inst_top(p : std_logic) return boolean is
+ begin
+ return (p = '0'); -- inverter
+ end function;
+
+ function conv_top_inst(p : boolean) return std_logic is
+ begin
+ if (p = FALSE) then
+ return '0'; -- identity
+ elsif (p = TRUE) then
+ return '1'; -- identity
+ else
+ return 'X'; -- error
+ end if;
+ end function;
+begin
+ A <= TRUE;
+
+ inst : entity work.ex1_entity
+ port map (
+ conv_inst_top(X) => conv_top_inst(A)
+ );
+end architecture;
diff --git a/testsuite/gna/issue265/testsuite.sh b/testsuite/gna/issue265/testsuite.sh
new file mode 100755
index 000000000..ac10ad9fd
--- /dev/null
+++ b/testsuite/gna/issue265/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze ex1_entity.vhdl ex1_top.vhdl
+elab_simulate_failure ex1_top
+
+clean
+
+echo "Test successful"