fix 'occured' typo

4 files changed, 503 insertions, 503 deletions

diff --git a/testsuite/gna/bug037/bugreport.txt b/testsuite/gna/bug037/bugreport.txt
index 0f61af22e..728876d61 100644
--- a/testsuite/gna/bug037/bugreport.txt
+++ b/testsuite/gna/bug037/bugreport.txt
@@ -1,191 +1,191 @@
-# 

-# Bug report created by PoC

-# 

-# Assemble files for the bug report....

-# execute these lines in PowerShell to gather all needed files

-# 

-mkdir H:\Austausch\PoC\temp\bugreport | cd

-cp H:\Austausch\PoC\tb\common\my_config_ML505.vhdl .

-cp H:\Austausch\PoC\tb\common\my_project.vhdl .

-cp H:\Austausch\PoC\src\common\utils.vhdl .

-cp H:\Austausch\PoC\src\common\config.vhdl .

-cp H:\Austausch\PoC\src\common\strings.vhdl .

-cp H:\Austausch\PoC\src\common\vectors.vhdl .

-cp H:\Austausch\PoC\src\common\physical.vhdl .

-cp H:\Austausch\PoC\src\sim\sim_types.vhdl .

-cp H:\Austausch\PoC\src\sim\sim_protected.v08.vhdl .

-cp H:\Austausch\PoC\src\sim\sim_global.v08.vhdl .

-cp H:\Austausch\PoC\src\sim\sim_simulation.v08.vhdl .

-cp H:\Austausch\PoC\src\arith\arith.pkg.vhdl .

-cp H:\Austausch\PoC\src\arith\arith_addw.vhdl .

-cp H:\Austausch\PoC\tb\arith\arith_addw_tb.vhdl .

-

-

-#

-# ATTENATION: This test requires Xilinx ISE unisim compiled into the folder ./xilinx

-#

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./my_config_ML505.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./my_project.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./utils.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./config.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./strings.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./vectors.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./physical.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_types.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_protected.v08.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_global.v08.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_simulation.v08.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./arith.pkg.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./arith_addw.vhdl

-ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=test ./arith_addw_tb.vhdl

-

-# excepted runtime circa 2 minutes

-ghdl.exe -r --syn-binding -fpsl -v -Pxilinx --std=08 --work=test arith_addw_tb --ieee-asserts=disable-at-0 --wave=H:\Austausch\PoC\temp\ghdl\arith_addw_tb.ghw

-

-# Generated output

---------------------------------------------------------------------------------

-Linking in memory

-Starting simulation

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-

-******************** GHDL Bug occured ****************************

-Please report this bug on https://github.com/tgingold/ghdl/issues

-GHDL release: GHDL 0.34dev (commit: 2016-01-20;  git branch: paebbels/llvm';  hash: 3a8fd5b) [Dunoon edition]

-Compiled with GNAT Version: GPL 2015 (20150428-49)

-In directory: H:\Austausch\PoC\temp\ghdl\

-Command line:

-C:\Tools\GHDL.new\bin\ghdl.exe -r --syn-binding -fpsl -v -Pxilinx --std=08 --work=test arith_addw_tb --ieee-asserts=disable-at-0 --wave=H:\Austausch\PoC\temp\ghdl\arith_addw_tb.ghw

-Exception CONSTRAINT_ERROR raised

-Exception information:

-Exception name: CONSTRAINT_ERROR

-Message: grt-waves.adb:1245 access check failed

-******************************************************************

-

---------------------------------------------------------------------------------

-#

-#

-# Expected Output

-#

-

---------------------------------------------------------------------------------

-Linking in memory

-Starting simulation

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk

-H:\Austausch\PoC\src\sim\sim_simulation.v08.vhdl:232:16:@0ms:(report note): simGenerateClock: (Instance: ':poc:simulation:simgenerateclock[std_logic,time,t_phase,t_dutycycle,t_wander]:clock')

-Period: 10000000 fs

-Phase: 0 second

-DutyCycle: 500000000 ppb

-PhaseAsFactor: 0.0

-WanderAsFactor: 0.0

-DutyCycleAsFactor: 5.0e-1

-Delay: 0 fs

-TimeHigh: 5000000 fs

-TimeLow: 5000000 fs

-

-========================================

-POC TESTBENCH REPORT

-========================================

-Assertions   16777216

-  failed     0

-Processes    1

-  active     0

-Tests        32

-     0: Test setup: ARCH=aam  SKIPPING=plain   P_INCLUSIVE=false

-     1: Test setup: ARCH=aam  SKIPPING=plain   P_INCLUSIVE=true

-     2: Test setup: ARCH=aam  SKIPPING=ccc     P_INCLUSIVE=false

-     3: Test setup: ARCH=aam  SKIPPING=ccc     P_INCLUSIVE=true

-     4: Test setup: ARCH=aam  SKIPPING=ppn_ks  P_INCLUSIVE=false

-     5: Test setup: ARCH=aam  SKIPPING=ppn_ks  P_INCLUSIVE=true

-     6: Test setup: ARCH=aam  SKIPPING=ppn_bk  P_INCLUSIVE=false

-     7: Test setup: ARCH=aam  SKIPPING=ppn_bk  P_INCLUSIVE=true

-     8: Test setup: ARCH=cai  SKIPPING=plain   P_INCLUSIVE=false

-     9: Test setup: ARCH=cai  SKIPPING=plain   P_INCLUSIVE=true

-    10: Test setup: ARCH=cai  SKIPPING=ccc     P_INCLUSIVE=false

-    11: Test setup: ARCH=cai  SKIPPING=ccc     P_INCLUSIVE=true

-    12: Test setup: ARCH=cai  SKIPPING=ppn_ks  P_INCLUSIVE=false

-    13: Test setup: ARCH=cai  SKIPPING=ppn_ks  P_INCLUSIVE=true

-    14: Test setup: ARCH=cai  SKIPPING=ppn_bk  P_INCLUSIVE=false

-    15: Test setup: ARCH=cai  SKIPPING=ppn_bk  P_INCLUSIVE=true

-    16: Test setup: ARCH=cca  SKIPPING=plain   P_INCLUSIVE=false

-    17: Test setup: ARCH=cca  SKIPPING=plain   P_INCLUSIVE=true

-    18: Test setup: ARCH=cca  SKIPPING=ccc     P_INCLUSIVE=false

-    19: Test setup: ARCH=cca  SKIPPING=ccc     P_INCLUSIVE=true

-    20: Test setup: ARCH=cca  SKIPPING=ppn_ks  P_INCLUSIVE=false

-    21: Test setup: ARCH=cca  SKIPPING=ppn_ks  P_INCLUSIVE=true

-    22: Test setup: ARCH=cca  SKIPPING=ppn_bk  P_INCLUSIVE=false

-    23: Test setup: ARCH=cca  SKIPPING=ppn_bk  P_INCLUSIVE=true

-    24: Test setup: ARCH=pai  SKIPPING=plain   P_INCLUSIVE=false

-    25: Test setup: ARCH=pai  SKIPPING=plain   P_INCLUSIVE=true

-    26: Test setup: ARCH=pai  SKIPPING=ccc     P_INCLUSIVE=false

-    27: Test setup: ARCH=pai  SKIPPING=ccc     P_INCLUSIVE=true

-    28: Test setup: ARCH=pai  SKIPPING=ppn_ks  P_INCLUSIVE=false

-    29: Test setup: ARCH=pai  SKIPPING=ppn_ks  P_INCLUSIVE=true

-    30: Test setup: ARCH=pai  SKIPPING=ppn_bk  P_INCLUSIVE=false

-    31: Test setup: ARCH=pai  SKIPPING=ppn_bk  P_INCLUSIVE=true

-========================================

-SIMULATION RESULT = PASSED

-========================================

-

---------------------------------------------------------------------------------

+# 
+# Bug report created by PoC
+# 
+# Assemble files for the bug report....
+# execute these lines in PowerShell to gather all needed files
+# 
+mkdir H:\Austausch\PoC\temp\bugreport | cd
+cp H:\Austausch\PoC\tb\common\my_config_ML505.vhdl .
+cp H:\Austausch\PoC\tb\common\my_project.vhdl .
+cp H:\Austausch\PoC\src\common\utils.vhdl .
+cp H:\Austausch\PoC\src\common\config.vhdl .
+cp H:\Austausch\PoC\src\common\strings.vhdl .
+cp H:\Austausch\PoC\src\common\vectors.vhdl .
+cp H:\Austausch\PoC\src\common\physical.vhdl .
+cp H:\Austausch\PoC\src\sim\sim_types.vhdl .
+cp H:\Austausch\PoC\src\sim\sim_protected.v08.vhdl .
+cp H:\Austausch\PoC\src\sim\sim_global.v08.vhdl .
+cp H:\Austausch\PoC\src\sim\sim_simulation.v08.vhdl .
+cp H:\Austausch\PoC\src\arith\arith.pkg.vhdl .
+cp H:\Austausch\PoC\src\arith\arith_addw.vhdl .
+cp H:\Austausch\PoC\tb\arith\arith_addw_tb.vhdl .
+
+
+#
+# ATTENATION: This test requires Xilinx ISE unisim compiled into the folder ./xilinx
+#
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./my_config_ML505.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./my_project.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./utils.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./config.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./strings.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./vectors.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./physical.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_types.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_protected.v08.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_global.v08.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./sim_simulation.v08.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./arith.pkg.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=poc ./arith_addw.vhdl
+ghdl.exe -a -fexplicit -frelaxed-rules --warn-binding --no-vital-checks --mb-comments --syn-binding -fpsl -v -Pxilinx --ieee=standard --std=08 --work=test ./arith_addw_tb.vhdl
+
+# excepted runtime circa 2 minutes
+ghdl.exe -r --syn-binding -fpsl -v -Pxilinx --std=08 --work=test arith_addw_tb --ieee-asserts=disable-at-0 --wave=H:\Austausch\PoC\temp\ghdl\arith_addw_tb.ghw
+
+# Generated output
+--------------------------------------------------------------------------------
+Linking in memory
+Starting simulation
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+
+******************** GHDL Bug occurred ****************************
+Please report this bug on https://github.com/tgingold/ghdl/issues
+GHDL release: GHDL 0.34dev (commit: 2016-01-20;  git branch: paebbels/llvm';  hash: 3a8fd5b) [Dunoon edition]
+Compiled with GNAT Version: GPL 2015 (20150428-49)
+In directory: H:\Austausch\PoC\temp\ghdl\
+Command line:
+C:\Tools\GHDL.new\bin\ghdl.exe -r --syn-binding -fpsl -v -Pxilinx --std=08 --work=test arith_addw_tb --ieee-asserts=disable-at-0 --wave=H:\Austausch\PoC\temp\ghdl\arith_addw_tb.ghw
+Exception CONSTRAINT_ERROR raised
+Exception information:
+Exception name: CONSTRAINT_ERROR
+Message: grt-waves.adb:1245 access check failed
+******************************************************************
+
+--------------------------------------------------------------------------------
+#
+#
+# Expected Output
+#
+
+--------------------------------------------------------------------------------
+Linking in memory
+Starting simulation
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=aam, BLOCKING=asc[5,4], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=cca, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=plain
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ccc
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_ks
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+Implementing 9-bit wide adder: ARCH=pai, BLOCKING=desc[4,5], SKIPPING=ppn_bk
+H:\Austausch\PoC\src\sim\sim_simulation.v08.vhdl:232:16:@0ms:(report note): simGenerateClock: (Instance: ':poc:simulation:simgenerateclock[std_logic,time,t_phase,t_dutycycle,t_wander]:clock')
+Period: 10000000 fs
+Phase: 0 second
+DutyCycle: 500000000 ppb
+PhaseAsFactor: 0.0
+WanderAsFactor: 0.0
+DutyCycleAsFactor: 5.0e-1
+Delay: 0 fs
+TimeHigh: 5000000 fs
+TimeLow: 5000000 fs
+
+========================================
+POC TESTBENCH REPORT
+========================================
+Assertions   16777216
+  failed     0
+Processes    1
+  active     0
+Tests        32
+     0: Test setup: ARCH=aam  SKIPPING=plain   P_INCLUSIVE=false
+     1: Test setup: ARCH=aam  SKIPPING=plain   P_INCLUSIVE=true
+     2: Test setup: ARCH=aam  SKIPPING=ccc     P_INCLUSIVE=false
+     3: Test setup: ARCH=aam  SKIPPING=ccc     P_INCLUSIVE=true
+     4: Test setup: ARCH=aam  SKIPPING=ppn_ks  P_INCLUSIVE=false
+     5: Test setup: ARCH=aam  SKIPPING=ppn_ks  P_INCLUSIVE=true
+     6: Test setup: ARCH=aam  SKIPPING=ppn_bk  P_INCLUSIVE=false
+     7: Test setup: ARCH=aam  SKIPPING=ppn_bk  P_INCLUSIVE=true
+     8: Test setup: ARCH=cai  SKIPPING=plain   P_INCLUSIVE=false
+     9: Test setup: ARCH=cai  SKIPPING=plain   P_INCLUSIVE=true
+    10: Test setup: ARCH=cai  SKIPPING=ccc     P_INCLUSIVE=false
+    11: Test setup: ARCH=cai  SKIPPING=ccc     P_INCLUSIVE=true
+    12: Test setup: ARCH=cai  SKIPPING=ppn_ks  P_INCLUSIVE=false
+    13: Test setup: ARCH=cai  SKIPPING=ppn_ks  P_INCLUSIVE=true
+    14: Test setup: ARCH=cai  SKIPPING=ppn_bk  P_INCLUSIVE=false
+    15: Test setup: ARCH=cai  SKIPPING=ppn_bk  P_INCLUSIVE=true
+    16: Test setup: ARCH=cca  SKIPPING=plain   P_INCLUSIVE=false
+    17: Test setup: ARCH=cca  SKIPPING=plain   P_INCLUSIVE=true
+    18: Test setup: ARCH=cca  SKIPPING=ccc     P_INCLUSIVE=false
+    19: Test setup: ARCH=cca  SKIPPING=ccc     P_INCLUSIVE=true
+    20: Test setup: ARCH=cca  SKIPPING=ppn_ks  P_INCLUSIVE=false
+    21: Test setup: ARCH=cca  SKIPPING=ppn_ks  P_INCLUSIVE=true
+    22: Test setup: ARCH=cca  SKIPPING=ppn_bk  P_INCLUSIVE=false
+    23: Test setup: ARCH=cca  SKIPPING=ppn_bk  P_INCLUSIVE=true
+    24: Test setup: ARCH=pai  SKIPPING=plain   P_INCLUSIVE=false
+    25: Test setup: ARCH=pai  SKIPPING=plain   P_INCLUSIVE=true
+    26: Test setup: ARCH=pai  SKIPPING=ccc     P_INCLUSIVE=false
+    27: Test setup: ARCH=pai  SKIPPING=ccc     P_INCLUSIVE=true
+    28: Test setup: ARCH=pai  SKIPPING=ppn_ks  P_INCLUSIVE=false
+    29: Test setup: ARCH=pai  SKIPPING=ppn_ks  P_INCLUSIVE=true
+    30: Test setup: ARCH=pai  SKIPPING=ppn_bk  P_INCLUSIVE=false
+    31: Test setup: ARCH=pai  SKIPPING=ppn_bk  P_INCLUSIVE=true
+========================================
+SIMULATION RESULT = PASSED
+========================================
+
+--------------------------------------------------------------------------------
diff --git a/testsuite/gna/issue25/1_SecondaryUnit.vhdl b/testsuite/gna/issue25/1_SecondaryUnit.vhdl
index 731a88e94..dd3ee6ab0 100644
--- a/testsuite/gna/issue25/1_SecondaryUnit.vhdl
+++ b/testsuite/gna/issue25/1_SecondaryUnit.vhdl
@@ -1,58 +1,58 @@
--- This snippet causes an exception:

---	PS H:\Austausch\PoC\temp\bugreport> C:\Tools\GHDL.new\bin\ghdl.exe -a -v .\1_SecondaryUnit.vhd

---	.\1_SecondaryUnit.vhd:19:42: can't match physical literal with type physical type "t_angel"

---	are_trees_equal: cannot handle IIR_KIND_UNIT_DECLARATION (*std_standard*:1:1)

---	

---	******************** GHDL Bug occured ****************************

---	Please report this bug on https://github.com/tgingold/ghdl/issues

---	GHDL release: GHDL 0.34dev (commit: 2016-01-20;  git branch: paebbels/llvm';  hash: 3a8fd5b) [Dunoon edition]

---	Compiled with GNAT Version: GPL 2015 (20150428-49)

---	In directory: H:\Austausch\PoC\temp\bugreport\

---	Command line:

---	C:\Tools\GHDL.new\bin\ghdl.exe -a -v .\1_SecondaryUnit.vhd

---	Exception TYPES.INTERNAL_ERROR raised

---	Exception information:

---	Exception name: TYPES.INTERNAL_ERROR

---	Message: errorout.adb:66

---	******************************************************************

---

--- The "syntax" error is, that I forgot to rename '10 sec' in line 35

-

-package pkg is

-	type T_ANGEL is range INTEGER'low to INTEGER'high units

-		second;

-		minute	= 60 second;

-		deg			= 60 minute;

-	end units;

-	

-	subtype T_PHASE is T_ANGEL range	-360 deg to 360 deg;

-	

-	function test1(Phase : T_PHASE := 10 second) return T_PHASE;

-	procedure test2(signal output : out T_PHASE; input : T_PHASE := 10.0 second);

-end package;

-	

-package body pkg is

-	function test1(Phase : T_PHASE := 10 sec) return T_PHASE is

-	begin

-		return Phase + 1.0 deg;

-	end function;

-	

-	procedure test2(signal output : out T_PHASE; input : T_PHASE := 10.0 second) is

-	begin

-		output <= input;

-	end procedure;

-end package body;

-

-

-use			works.pkg.all;

-

-entity SecondaryUnit_tb is

-end entity;

-

-architecture test of SecondaryUnit_tb is

-	signal TestSignal1 : T_PHASE;

-	signal TestSignal2 : T_PHASE;

-begin

-	TestSignal1	<= test1(50.0 second);

-	test2(TestSignal2, TestSignal1);

-end architecture;

+-- This snippet causes an exception:
+--	PS H:\Austausch\PoC\temp\bugreport> C:\Tools\GHDL.new\bin\ghdl.exe -a -v .\1_SecondaryUnit.vhd
+--	.\1_SecondaryUnit.vhd:19:42: can't match physical literal with type physical type "t_angel"
+--	are_trees_equal: cannot handle IIR_KIND_UNIT_DECLARATION (*std_standard*:1:1)
+--	
+--	******************** GHDL Bug occurred ****************************
+--	Please report this bug on https://github.com/tgingold/ghdl/issues
+--	GHDL release: GHDL 0.34dev (commit: 2016-01-20;  git branch: paebbels/llvm';  hash: 3a8fd5b) [Dunoon edition]
+--	Compiled with GNAT Version: GPL 2015 (20150428-49)
+--	In directory: H:\Austausch\PoC\temp\bugreport\
+--	Command line:
+--	C:\Tools\GHDL.new\bin\ghdl.exe -a -v .\1_SecondaryUnit.vhd
+--	Exception TYPES.INTERNAL_ERROR raised
+--	Exception information:
+--	Exception name: TYPES.INTERNAL_ERROR
+--	Message: errorout.adb:66
+--	******************************************************************
+--
+-- The "syntax" error is, that I forgot to rename '10 sec' in line 35
+
+package pkg is
+	type T_ANGEL is range INTEGER'low to INTEGER'high units
+		second;
+		minute	= 60 second;
+		deg			= 60 minute;
+	end units;
+	
+	subtype T_PHASE is T_ANGEL range	-360 deg to 360 deg;
+	
+	function test1(Phase : T_PHASE := 10 second) return T_PHASE;
+	procedure test2(signal output : out T_PHASE; input : T_PHASE := 10.0 second);
+end package;
+	
+package body pkg is
+	function test1(Phase : T_PHASE := 10 sec) return T_PHASE is
+	begin
+		return Phase + 1.0 deg;
+	end function;
+	
+	procedure test2(signal output : out T_PHASE; input : T_PHASE := 10.0 second) is
+	begin
+		output <= input;
+	end procedure;
+end package body;
+
+
+use			works.pkg.all;
+
+entity SecondaryUnit_tb is
+end entity;
+
+architecture test of SecondaryUnit_tb is
+	signal TestSignal1 : T_PHASE;
+	signal TestSignal2 : T_PHASE;
+begin
+	TestSignal1	<= test1(50.0 second);
+	test2(TestSignal2, TestSignal1);
+end architecture;
diff --git a/testsuite/gna/issue38/bugreport_aliasprotected.vhdl b/testsuite/gna/issue38/bugreport_aliasprotected.vhdl
index 1483d55c8..f9091f5f3 100644
--- a/testsuite/gna/issue38/bugreport_aliasprotected.vhdl
+++ b/testsuite/gna/issue38/bugreport_aliasprotected.vhdl
@@ -1,172 +1,172 @@
--- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-

--- vim: tabstop=2:shiftwidth=2:noexpandtab

--- kate: tab-width 2; replace-tabs off; indent-width 2;

--- =============================================================================

--- Authors:					Patrick Lehmann

--- Reproducer:			Using aliases to protected type methods cause an exception.

--- 

--- License:

--- =============================================================================

--- Copyright 2007-2016 Technische Universitaet Dresden - Germany

---										 Chair for VLSI-Design, Diagnostics and Architecture

--- 

--- Licensed under the Apache License, Version 2.0 (the "License");

--- you may not use this file except in compliance with the License.

--- You may obtain a copy of the License at

--- 

---		http://www.apache.org/licenses/LICENSE-2.0

--- 

--- Unless required by applicable law or agreed to in writing, software

--- distributed under the License is distributed on an "AS IS" BASIS,

--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

--- See the License for the specific language governing permissions and

--- limitations under the License.

--- =============================================================================

---

--- Issue 1:

---	When analyzed in VHDL-93 mode an error is reported:

---		.\bugreport_aliasprotected.vhdl:4:26: protected type not allowed in vhdl87/93

---		.\bugreport_aliasprotected.vhdl:9:12: 'protected' is expected instead of 'protected'

---	Line 1 is perfectly clear, but what is the intension of line 2?

---	Is this follow up error necessary or should it have another message text?

---

--- Issue 2:

---	Calling an aliases to a shared variable's method causes an exception in GHDL:

---		******************** GHDL Bug occured ****************************

---		Please report this bug on https://github.com/tgingold/ghdl/issues

---		GHDL release: GHDL 0.34dev (commit: 2016-01-27;  git branch: paebbels/master';  hash: d424eb8) [Dunoon edition]

---		Compiled with GNAT Version: GPL 2015 (20150428-49)

---		In directory: H:\Austausch\PoC\temp\ghdl\

---		Command line:

---		C:\Tools\GHDL.new\bin\ghdl.exe -r --std=08 test

---		Exception TYPES.INTERNAL_ERROR raised

---		Exception information:

---		Exception name: TYPES.INTERNAL_ERROR

---		Message: trans.adb:487

---		******************************************************************

---	The alias definition by itself is not causing any errors. In my big example, I

---	could at least use an alias to a procedure without parameters. This short example

---	throws exceptions on all 4 variants (with/without parameter; with/without return value).

---

---	You can comment/uncomment the alias/wrapping function/procedure to cause the error.

---

--- GHDL calls:

---	PS> ghdl.exe -a --std=08 .\bugreport_aliasprotected.vhdl

---	PS> ghdl.exe -r --std=08 test

---

--- Expected output:

---	.\bugreport_aliasprotected.vhdl:163:16:@0ms:(report note): wrapGet:      7  expected: 7

---	.\bugreport_aliasprotected.vhdl:165:16:@0ms:(report note): wrapGet:      5  expected: 5

---	.\bugreport_aliasprotected.vhdl:166:16:@0ms:(report note): wrapExcahnge: 5  expected: 5

---	.\bugreport_aliasprotected.vhdl:167:16:@0ms:(report note): wrapGet:      3  expected: 3

---	.\bugreport_aliasprotected.vhdl:169:16:@0ms:(report note): wrapGet:      0  expected: 0

---	

--- =============================================================================

--- Protected type package

--- =============================================================================

-package pkg is

-	type T_INTEGER is protected

-		procedure				Clear;

-		procedure				Set(Value : INTEGER);

-		impure function	Get return INTEGER;

-		impure function	Exchange(Value : INTEGER) return INTEGER;

-	end protected;

-end package;

-

-package body pkg is

-	type T_INTEGER is protected body

-		variable LocalVariable	: INTEGER		:= 7;

-		

-		procedure Clear is

-		begin

-			LocalVariable		:= 0;

-		end procedure;

-		

-		procedure Set(Value : INTEGER) is

-		begin

-			LocalVariable		:= Value;

-		end procedure;

-		

-		impure function Get return INTEGER is

-		begin

-			return LocalVariable;

-		end function;

-		

-		impure function	Exchange(Value : INTEGER) return INTEGER is

-			variable Result	: INTEGER;

-		begin

-			Result				:= LocalVariable;

-			LocalVariable	:= Value;

-			return Result;

-		end function;

-	end protected body;

-end package body;

-

--- =============================================================================

--- Wrapper package

--- =============================================================================

-use work.pkg.all;

-

-package wrapper is

-	shared variable MyBoolean		: T_INTEGER;

-	

-	-- alias						wrapClear			is MyBoolean.Clear[];				-- if this alias is used, GHDL crashes

-	alias						wrapperClear	is MyBoolean.Clear[];				-- unused alias => no crash

-	procedure				wrapClear;																-- wrapped by a call chain => no crash

-	

-	-- alias						wrapSet				is MyBoolean.Set[INTEGER];

-	procedure				wrapSet(Value : INTEGER);

-	

-	-- alias						wrapGet				is MyBoolean.Get[return INTEGER];

-	impure function	wrapGet return INTEGER;

-	

-	-- alias						wrapExchange	is MyBoolean.Exchange[INTEGER return INTEGER];

-	impure function	wrapExchange(Value : INTEGER) return INTEGER;

-	

-end package;

-

-package body wrapper is

-	procedure wrapClear is

-	begin

-		MyBoolean.Clear;

-	end procedure;

-	

-	procedure wrapSet(Value : INTEGER) is

-	begin

-		MyBoolean.Set(Value);

-	end procedure;

-	

-	impure function wrapGet return INTEGER is

-	begin

-		return MyBoolean.Get;

-	end function;

-	

-	impure function	wrapExchange(Value : INTEGER) return INTEGER is

-	begin

-		return MyBoolean.Exchange(Value);

-	end function;

-end package body;

-

--- =============================================================================

--- Testbench

--- =============================================================================

-use work.wrapper.all;

-

-entity test is

-end entity;

-

-

-architecture tb of test is

-begin

-	process

-	begin

-		report "wrapGet:      " & INTEGER'image(wrapGet)					& "  expected: 7" severity NOTE;

-		wrapSet(5);

-		report "wrapGet:      " & INTEGER'image(wrapGet)					& "  expected: 5" severity NOTE;

-		report "wrapExcahnge: " & INTEGER'image(wrapExchange(3))	& "  expected: 5" severity NOTE;

-		report "wrapGet:      " & INTEGER'image(wrapGet)					& "  expected: 3" severity NOTE;

-		wrapperClear;

-		report "wrapGet:      " & INTEGER'image(wrapGet)					& "  expected: 0" severity NOTE;

-		wait;

-	end process;

-end architecture;

+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:					Patrick Lehmann
+-- Reproducer:			Using aliases to protected type methods cause an exception.
+-- 
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+--										 Chair for VLSI-Design, Diagnostics and Architecture
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--		http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+--
+-- Issue 1:
+--	When analyzed in VHDL-93 mode an error is reported:
+--		.\bugreport_aliasprotected.vhdl:4:26: protected type not allowed in vhdl87/93
+--		.\bugreport_aliasprotected.vhdl:9:12: 'protected' is expected instead of 'protected'
+--	Line 1 is perfectly clear, but what is the intension of line 2?
+--	Is this follow up error necessary or should it have another message text?
+--
+-- Issue 2:
+--	Calling an aliases to a shared variable's method causes an exception in GHDL:
+--		******************** GHDL Bug occurred ****************************
+--		Please report this bug on https://github.com/tgingold/ghdl/issues
+--		GHDL release: GHDL 0.34dev (commit: 2016-01-27;  git branch: paebbels/master';  hash: d424eb8) [Dunoon edition]
+--		Compiled with GNAT Version: GPL 2015 (20150428-49)
+--		In directory: H:\Austausch\PoC\temp\ghdl\
+--		Command line:
+--		C:\Tools\GHDL.new\bin\ghdl.exe -r --std=08 test
+--		Exception TYPES.INTERNAL_ERROR raised
+--		Exception information:
+--		Exception name: TYPES.INTERNAL_ERROR
+--		Message: trans.adb:487
+--		******************************************************************
+--	The alias definition by itself is not causing any errors. In my big example, I
+--	could at least use an alias to a procedure without parameters. This short example
+--	throws exceptions on all 4 variants (with/without parameter; with/without return value).
+--
+--	You can comment/uncomment the alias/wrapping function/procedure to cause the error.
+--
+-- GHDL calls:
+--	PS> ghdl.exe -a --std=08 .\bugreport_aliasprotected.vhdl
+--	PS> ghdl.exe -r --std=08 test
+--
+-- Expected output:
+--	.\bugreport_aliasprotected.vhdl:163:16:@0ms:(report note): wrapGet:      7  expected: 7
+--	.\bugreport_aliasprotected.vhdl:165:16:@0ms:(report note): wrapGet:      5  expected: 5
+--	.\bugreport_aliasprotected.vhdl:166:16:@0ms:(report note): wrapExcahnge: 5  expected: 5
+--	.\bugreport_aliasprotected.vhdl:167:16:@0ms:(report note): wrapGet:      3  expected: 3
+--	.\bugreport_aliasprotected.vhdl:169:16:@0ms:(report note): wrapGet:      0  expected: 0
+--	
+-- =============================================================================
+-- Protected type package
+-- =============================================================================
+package pkg is
+	type T_INTEGER is protected
+		procedure				Clear;
+		procedure				Set(Value : INTEGER);
+		impure function	Get return INTEGER;
+		impure function	Exchange(Value : INTEGER) return INTEGER;
+	end protected;
+end package;
+
+package body pkg is
+	type T_INTEGER is protected body
+		variable LocalVariable	: INTEGER		:= 7;
+		
+		procedure Clear is
+		begin
+			LocalVariable		:= 0;
+		end procedure;
+		
+		procedure Set(Value : INTEGER) is
+		begin
+			LocalVariable		:= Value;
+		end procedure;
+		
+		impure function Get return INTEGER is
+		begin
+			return LocalVariable;
+		end function;
+		
+		impure function	Exchange(Value : INTEGER) return INTEGER is
+			variable Result	: INTEGER;
+		begin
+			Result				:= LocalVariable;
+			LocalVariable	:= Value;
+			return Result;
+		end function;
+	end protected body;
+end package body;
+
+-- =============================================================================
+-- Wrapper package
+-- =============================================================================
+use work.pkg.all;
+
+package wrapper is
+	shared variable MyBoolean		: T_INTEGER;
+	
+	-- alias						wrapClear			is MyBoolean.Clear[];				-- if this alias is used, GHDL crashes
+	alias						wrapperClear	is MyBoolean.Clear[];				-- unused alias => no crash
+	procedure				wrapClear;																-- wrapped by a call chain => no crash
+	
+	-- alias						wrapSet				is MyBoolean.Set[INTEGER];
+	procedure				wrapSet(Value : INTEGER);
+	
+	-- alias						wrapGet				is MyBoolean.Get[return INTEGER];
+	impure function	wrapGet return INTEGER;
+	
+	-- alias						wrapExchange	is MyBoolean.Exchange[INTEGER return INTEGER];
+	impure function	wrapExchange(Value : INTEGER) return INTEGER;
+	
+end package;
+
+package body wrapper is
+	procedure wrapClear is
+	begin
+		MyBoolean.Clear;
+	end procedure;
+	
+	procedure wrapSet(Value : INTEGER) is
+	begin
+		MyBoolean.Set(Value);
+	end procedure;
+	
+	impure function wrapGet return INTEGER is
+	begin
+		return MyBoolean.Get;
+	end function;
+	
+	impure function	wrapExchange(Value : INTEGER) return INTEGER is
+	begin
+		return MyBoolean.Exchange(Value);
+	end function;
+end package body;
+
+-- =============================================================================
+-- Testbench
+-- =============================================================================
+use work.wrapper.all;
+
+entity test is
+end entity;
+
+
+architecture tb of test is
+begin
+	process
+	begin
+		report "wrapGet:      " & INTEGER'image(wrapGet)					& "  expected: 7" severity NOTE;
+		wrapSet(5);
+		report "wrapGet:      " & INTEGER'image(wrapGet)					& "  expected: 5" severity NOTE;
+		report "wrapExcahnge: " & INTEGER'image(wrapExchange(3))	& "  expected: 5" severity NOTE;
+		report "wrapGet:      " & INTEGER'image(wrapGet)					& "  expected: 3" severity NOTE;
+		wrapperClear;
+		report "wrapGet:      " & INTEGER'image(wrapGet)					& "  expected: 0" severity NOTE;
+		wait;
+	end process;
+end architecture;
diff --git a/testsuite/gna/issue42/bugreport_attribute.vhdl b/testsuite/gna/issue42/bugreport_attribute.vhdl
index a99d11263..36eab55d2 100644
--- a/testsuite/gna/issue42/bugreport_attribute.vhdl
+++ b/testsuite/gna/issue42/bugreport_attribute.vhdl
@@ -1,82 +1,82 @@
--- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-

--- vim: tabstop=2:shiftwidth=2:noexpandtab

--- kate: tab-width 2; replace-tabs off; indent-width 2;

--- =============================================================================

--- Authors:					Patrick Lehmann

--- Reproducer:			Experiments on custom attributes ended in a crash.

--- 

--- License:

--- =============================================================================

--- Copyright 2007-2016 Technische Universitaet Dresden - Germany

---										 Chair for VLSI-Design, Diagnostics and Architecture

--- 

--- Licensed under the Apache License, Version 2.0 (the "License");

--- you may not use this file except in compliance with the License.

--- You may obtain a copy of the License at

--- 

---		http://www.apache.org/licenses/LICENSE-2.0

--- 

--- Unless required by applicable law or agreed to in writing, software

--- distributed under the License is distributed on an "AS IS" BASIS,

--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

--- See the License for the specific language governing permissions and

--- limitations under the License.

--- =============================================================================

---

--- Issue:

---	I'm not sure if my experimental code is allowed in VHDL, but it let GHDL

---	crash. So I'm reporting just an unhandled exception.

---

---	GHDL's output is:

---		.\attribute.vhdl:64:58: can't match 'image attribute with type character

---		.\attribute.vhdl:64:53: (location of 'image attribute)

---		finish_sem_name: cannot handle IIR_KIND_OVERLOAD_LIST (??:??:??)

---		

---		******************** GHDL Bug occured ****************************

---		Please report this bug on https://github.com/tgingold/ghdl/issues

---		GHDL release: GHDL 0.34dev (commit: 2016-02-11;  git branch: paebbels/master';  hash: f24fdfb) [Dunoon edition]

---		Compiled with GNAT Version: GPL 2015 (20150428-49)

---		In directory: H:\Austausch\PoC\temp\ghdl\

---		Command line:

---		C:\Tools\GHDL.new\bin\ghdl.exe -a --std=08 .\attribute.vhdl

---		Exception TYPES.INTERNAL_ERROR raised

---		Exception information:

---		Exception name: TYPES.INTERNAL_ERROR

---		Message: errorout.adb:66

---		******************************************************************

---

--- GHDL calls:

---	PS> ghdl.exe -a --std=93c .\attribute.vhdl

---	PS> ghdl.exe -a --std=08 .\attribute.vhdl

---	

-library IEEE;

-use			IEEE.std_logic_1164.all;

-

-

-entity test is

-end entity;

-

-architecture tb of test is

-	function to_string(slv : STD_LOGIC_VECTOR) return STRING is

-		variable Result		: STRING(slv'length - 1 downto 0);

-	begin

-		for i in slv'range loop

-			Result(i + 1)	:= STD_LOGIC'image(slv(i));

-		end loop;

-		return Result;

-	end function;

-	

-	attribute serialize		: to_string;

-	

-	signal mySignal		: STD_LOGIC_VECTOR(7 downto 0);

-	attribute serialize of mySignal		: signal is to_string[STD_LOGIC_VECTOR return STRING];

-	

-begin

-	mySignal		<= x"24";

-

-	process

-	begin

-		report "mySignal=" & mySignal'serialize severity NOTE;

-		wait;

-	end process;

-end architecture;

+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:					Patrick Lehmann
+-- Reproducer:			Experiments on custom attributes ended in a crash.
+-- 
+-- License:
+-- =============================================================================
+-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
+--										 Chair for VLSI-Design, Diagnostics and Architecture
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--		http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+--
+-- Issue:
+--	I'm not sure if my experimental code is allowed in VHDL, but it let GHDL
+--	crash. So I'm reporting just an unhandled exception.
+--
+--	GHDL's output is:
+--		.\attribute.vhdl:64:58: can't match 'image attribute with type character
+--		.\attribute.vhdl:64:53: (location of 'image attribute)
+--		finish_sem_name: cannot handle IIR_KIND_OVERLOAD_LIST (??:??:??)
+--		
+--		******************** GHDL Bug occurred ****************************
+--		Please report this bug on https://github.com/tgingold/ghdl/issues
+--		GHDL release: GHDL 0.34dev (commit: 2016-02-11;  git branch: paebbels/master';  hash: f24fdfb) [Dunoon edition]
+--		Compiled with GNAT Version: GPL 2015 (20150428-49)
+--		In directory: H:\Austausch\PoC\temp\ghdl\
+--		Command line:
+--		C:\Tools\GHDL.new\bin\ghdl.exe -a --std=08 .\attribute.vhdl
+--		Exception TYPES.INTERNAL_ERROR raised
+--		Exception information:
+--		Exception name: TYPES.INTERNAL_ERROR
+--		Message: errorout.adb:66
+--		******************************************************************
+--
+-- GHDL calls:
+--	PS> ghdl.exe -a --std=93c .\attribute.vhdl
+--	PS> ghdl.exe -a --std=08 .\attribute.vhdl
+--	
+library IEEE;
+use			IEEE.std_logic_1164.all;
+
+
+entity test is
+end entity;
+
+architecture tb of test is
+	function to_string(slv : STD_LOGIC_VECTOR) return STRING is
+		variable Result		: STRING(slv'length - 1 downto 0);
+	begin
+		for i in slv'range loop
+			Result(i + 1)	:= STD_LOGIC'image(slv(i));
+		end loop;
+		return Result;
+	end function;
+	
+	attribute serialize		: to_string;
+	
+	signal mySignal		: STD_LOGIC_VECTOR(7 downto 0);
+	attribute serialize of mySignal		: signal is to_string[STD_LOGIC_VECTOR return STRING];
+	
+begin
+	mySignal		<= x"24";
+
+	process
+	begin
+		report "mySignal=" & mySignal'serialize severity NOTE;
+		wait;
+	end process;
+end architecture;