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authorTristan Gingold <tgingold@free.fr>2019-07-09 05:15:27 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-09 05:15:27 +0200
commit0926686937d3c673f46cd0d5c770a7fd4744a47d (patch)
treecc4e24838e2a65555db657368a706f7ae3a8f26f /testsuite/gna/issue864/mwe2.vhdl
parentf722968eeda135aeb50d287b6d83627763191323 (diff)
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Add testcase for #864
Diffstat (limited to 'testsuite/gna/issue864/mwe2.vhdl')
-rw-r--r--testsuite/gna/issue864/mwe2.vhdl40
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diff --git a/testsuite/gna/issue864/mwe2.vhdl b/testsuite/gna/issue864/mwe2.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a is
+ port (
+ a_in : IN std_logic;
+ a_out : OUT std_logic
+ );
+end entity a;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity b is
+ port (
+ b_in : IN std_logic;
+ b_out : OUT std_logic
+ );
+end entity b;
+
+architecture rtl of a is
+begin
+ process (a_in)
+ begin
+ a_out <= a_in;
+ end process;
+end architecture rtl;
+
+architecture rtl of b is
+ component a
+ port (
+ a_in : IN std_logic;
+ a_out : OUT std_logic
+ );
+ end component;
+
+ for a0 : a;
+begin
+ a0: a port map (a_in => b_in, a_out => b_out);
+end architecture rtl;